Just a couple high-level comments: Is this code entirely written by you?
If the code is i386-specific, I'd like to see it put into i386 namespace. The use of bitfields worries me, especially if the code might be ported to other architectures. I can see now why you put __packed__ on all your structs, as it is necessary to get anywhere close to the right behavior from the compiler when using bit fields. -Gedare On Wed, Nov 12, 2014 at 10:07 AM, Jan Dolezal <dolez...@fel.cvut.cz> wrote: > --- > c/src/lib/libbsp/i386/pc386/Makefile.am | 2 + > c/src/lib/libbsp/i386/pc386/include/edid.h | 759 > +++++++++++++++++++++++++++++ > c/src/lib/libbsp/i386/pc386/include/vbe3.h | 461 ++++++++++++++++++ > c/src/lib/libbsp/i386/pc386/preinstall.am | 8 + > 4 files changed, 1230 insertions(+) > create mode 100644 c/src/lib/libbsp/i386/pc386/include/edid.h > create mode 100644 c/src/lib/libbsp/i386/pc386/include/vbe3.h > > diff --git a/c/src/lib/libbsp/i386/pc386/Makefile.am > b/c/src/lib/libbsp/i386/pc386/Makefile.am > index 6042b5b..2e60947 100644 > --- a/c/src/lib/libbsp/i386/pc386/Makefile.am > +++ b/c/src/lib/libbsp/i386/pc386/Makefile.am > @@ -106,6 +106,8 @@ libbsp_a_SOURCES += console/printk_support.c > libbsp_a_SOURCES += console/vgacons.c > libbsp_a_SOURCES += console/exar17d15x.c > libbsp_a_SOURCES += console/rtd316.c > +include_HEADERS += include/vbe3.h > +include_HEADERS += include/edid.h > if USE_CIRRUS_GD5446 > libbsp_a_SOURCES += console/fb_cirrus.c > else > diff --git a/c/src/lib/libbsp/i386/pc386/include/edid.h > b/c/src/lib/libbsp/i386/pc386/include/edid.h > new file mode 100644 > index 0000000..937976e > --- /dev/null > +++ b/c/src/lib/libbsp/i386/pc386/include/edid.h > @@ -0,0 +1,759 @@ > +/** > + * @file edid.h > + * > + * @ingroup i386_pc386 > + * > + * @brief VESA EDID definitions. > + */ > + > +/* > + * edid.h - This file contains definitions for constants related to > + * VESA Extended Display Identification Data. > + * More information can be found at > + * <http://www.vesa.org/vesa-standards/free-standards/> > + * VESA public standards may be found at > + * <http://www.vesa.org/wp-content/uploads/2010/12/thankspublic.htm> > + * > + * Copyright (C) 2014 Jan Doležal (dolez...@fel.cvut.cz) > + * CTU in Prague. > + * > + * The license and distribution terms for this file may be > + * found in the file LICENSE in this distribution or at > + * http://www.rtems.org/license/LICENSE. > + */ > + > +#ifndef _EDID_H > +#define _EDID_H > + > +#ifndef ASM /* ASM */ > + > +#include <stdint.h> > + > +#ifdef __cplusplus > +extern "C" { > +#endif /* __cplusplus */ > + > + > +/* VESA Extended Display Identification Data (EDID) Standard > + Version 3, Revision Date: November 13, 1997 */ > +/* VESA Enhanced Extended Display Identification Data (E-EDID) Standard > + Release A, Revision 2, September 25, 2006 */ > +/* VESA Enhanced Extended Display Identification Data (E-EDID) Proposed > + Release A, March 27, 2007 */ > + > +/**** structs and defines shared by both EDIDv1 and EDIDv2 ****/ > + > +/* Video Input Definition */ > +/* Analog Interface Data Format - Signal Level Standard */ > +#define EDIDx_SLS_0700_0300_1000Vpp 0x0 > +#define EDIDx_SLS_0714_0286_1000Vpp 0x1 > +#define EDIDx_SLS_1000_0400_1400Vpp 0x2 > +#define EDIDx_SLS_0700_0000_0700Vpp 0x3 > + > +struct DetailedTimingDescriptor{ > + uint16_t PixelClock_div10000; > + uint8_t HorizontalActiveLow; > + uint8_t HorizontalBlankingLow; > + uint8_t HorizontalBlankingHigh : 4; > + uint8_t HorizontalActiveHigh : 4; > + uint8_t VerticalActiveLow; > + uint8_t VerticalBlankingLow; > + uint8_t VerticalBlankingHigh : 4; > + uint8_t VerticalActiveHigh : 4; > + uint8_t HorizontalSyncOffsetLow; > + uint8_t HorizontalSyncPulseWidthLow; > + uint8_t VerticalSyncPulseWidthLow : 4; > + uint8_t VerticalSyncOffsetLow : 4; > + uint8_t VerticalSyncPulseWidthHigh : 2; > + uint8_t VerticalSyncOffsetHigh : 2; > + uint8_t HorizontalSyncPulseWidthHigh : 2; > + uint8_t HorizontalSyncOffsetHigh : 2; > + uint8_t HorizontalImageSizeLow; > + uint8_t VerticalImageSizeLow; > + uint8_t VerticalImageSizeHigh : 4; > + uint8_t HorizontalImageSizeHigh : 4; > + uint8_t HorizontalBorder; > + uint8_t VerticalBorder; > + uint8_t Flag_StereoMode0 : 1; > +/* next four flags has different purpose with analog > + and digital interfaces for EDID version 2; first > + goes analog, after underscore there is digital name of bit */ > + uint8_t Flag_SyncPolarity_LPPolarity : 1; > + uint8_t Flag_Serration_FLMPolarity : 1; > + uint8_t Flag_Composition_Serration : 1; > + uint8_t Flag_Composition_ShiftClockUse : 1; > + > + uint8_t Flag_StereoMode1 : 2; > + uint8_t Flag_Interlaced : 1; > +}__attribute__((__packed__)); > + > +struct ColorPointData { > + uint8_t ColorPointWhitePointIndexNumber; > + uint8_t ColorPointWhiteLowBits; > + uint8_t ColorPointWhite_x; > + uint8_t ColorPointWhite_y; > + uint8_t ColorPointWhiteGamma; > +}__attribute__((__packed__)); > + > +/**** structs and defines for EDIDv1 ****/ > + > +/* Basic Display Parameters */ > + /* Feature Support */ > + /* analog - Display Color Type */ > +#define EDID_DisplayType_Monochrome 0 > +#define EDID_DisplayType_RGBcolor 1 > +#define EDID_DisplayType_nonRGBcolor 2 > +#define EDID_DisplayType_undef 3 > + /* digital - Supported Color Encoding Formats */ > +#define EDID_DisplayType_RGB444 0 > +#define EDID_DisplayType_RGB444YCrCb444 1 > +#define EDID_DisplayType_RGB444YCrCb422 2 > +#define EDID_DisplayType_RGB444YCrCb444YCrCb422 3 > + > +/* Monitor Descriptor - Data Type Tag */ > +#define EDID_DTT_MonitorSerialNumber 0xFF > + > +#define EDID_DTT_ASCIIString 0xFE > + > +#define EDID_DTT_MonitorRangeLimits 0xFD > +struct MonitorRangeLimits { > + uint8_t MinVerticalRateInHz; > + uint8_t MaxVerticalRateInHz; > + uint8_t MinHorizontalInKHz; > + uint8_t MaxHorizontalInKHz; > + uint8_t MaxSupportedPixelClockIn10MHz; > +/* see VESA, Generalized Timing Formula Standard - GTF > + Version 1.0, December 18, 1996 */ > + uint8_t GTFStandard[8]; > +}__attribute__((__packed__)); > + > +#define EDID_DTT_MonitorName 0xFC > + > +#define EDID_DTT_AdditionalColorPointData 0xFB > +/* Standard Timing Identification */ > +#define EDID_DTT_AdditionalSTI 0xFA > + > +#define EDID_DTT_DisplayColorManagement 0xF9 > + > +#define EDID_DTT_CVT3ByteTimingCodes 0xF8 > +#define EDID_CVT_AspectRatio_4_3 0 > +#define EDID_CVT_AspectRatio_16_9 1 > +#define EDID_CVT_AspectRatio_16_10 2 > +#define EDID_CVT_AspectRatio_15_9 3 > +#define EDID_CVT_PrefVertRate50Hz 0 > +#define EDID_CVT_PrefVertRate60Hz 1 > +#define EDID_CVT_PrefVertRate75Hz 2 > +#define EDID_CVT_PrefVertRate85Hz 3 > +struct CVT3ByteCodeDescriptor { > + uint8_t AddressableLinesLow; > + uint8_t Reserved0 : 2; > + uint8_t AspectRatio : 2; > + uint8_t AddressableLinesHigh : 4; > + /* next 5 bits indicate supported vertical rates */ > + uint8_t VerticalRate60HzRB : 1; > + uint8_t VerticalRate85Hz : 1; > + uint8_t VerticalRate75Hz : 1; > + uint8_t VerticalRate60Hz : 1; > + uint8_t VerticalRate50Hz : 1; > + uint8_t PreferredVerticalRate : 2; > + uint8_t Reserved1 : 1; > +}__attribute__((__packed__)); > +struct CVTTimingCodes3B { > + uint8_t VersionNumber; > + struct CVT3ByteCodeDescriptor cvt[4]; > +}__attribute__((__packed__)); > + > +#define EDID_DTT_EstablishedTimingsIII 0xF7 > +struct EstablishedTimingsIII { > + uint8_t RevisionNumber; > + > + uint8_t EST_1152x864_75Hz : 1; > + uint8_t EST_1024x768_85Hz : 1; > + uint8_t EST_800x600_85Hz : 1; > + uint8_t EST_848x480_60Hz : 1; > + uint8_t EST_640x480_85Hz : 1; > + uint8_t EST_720x400_85Hz : 1; > + uint8_t EST_640x400_85Hz : 1; > + uint8_t EST_640x350_85Hz : 1; > + > + uint8_t EST_1280x1024_85Hz : 1; > + uint8_t EST_1280x1024_60Hz : 1; > + uint8_t EST_1280x960_85Hz : 1; > + uint8_t EST_1280x960_60Hz : 1; > + uint8_t EST_1280x768_85Hz : 1; > + uint8_t EST_1280x768_75Hz : 1; > + uint8_t EST_1280x768_60Hz : 1; > + uint8_t EST_1280x768_60HzRB : 1; > + > + uint8_t EST_1400x1050_75Hz : 1; > + uint8_t EST_1400x1050_60Hz : 1; > + uint8_t EST_1400x1050_60HzRB: 1; > + uint8_t EST_1400x900_85Hz : 1; > + uint8_t EST_1400x900_75Hz : 1; > + uint8_t EST_1400x900_60Hz : 1; > + uint8_t EST_1400x900_60HzRB : 1; > + uint8_t EST_1360x768_60Hz : 1; > + > + uint8_t EST_1600x1200_70Hz : 1; > + uint8_t EST_1600x1200_65Hz : 1; > + uint8_t EST_1600x1200_60Hz : 1; > + uint8_t EST_1680x1050_85Hz : 1; > + uint8_t EST_1680x1050_75Hz : 1; > + uint8_t EST_1680x1050_60Hz : 1; > + uint8_t EST_1680x1050_60HzRB: 1; > + uint8_t EST_1400x1050_85Hz : 1; > + > + uint8_t EST_1920x1200_60Hz : 1; > + uint8_t EST_1920x1200_60HzRB: 1; > + uint8_t EST_1856x1392_75Hz : 1; > + uint8_t EST_1856x1392_60Hz : 1; > + uint8_t EST_1792x1344_75Hz : 1; > + uint8_t EST_1792x1344_60Hz : 1; > + uint8_t EST_1600x1200_85Hz : 1; > + uint8_t EST_1600x1200_75Hz : 1; > + > + uint8_t EST_Reserved0 : 4; > + uint8_t EST_1920x1440_75Hz : 1; > + uint8_t EST_1920x1440_60Hz : 1; > + uint8_t EST_1920x1200_85Hz : 1; > + uint8_t EST_1920x1200_75Hz : 1; > + > + uint8_t EST_Reserved1[6]; > +}__attribute__((__packed__)); > + > +#define EDID_DTT_DescriptorSpaceUnused 0x10 > +/* DTT 0x0 - 0xF are manufacturer specific */ > + > +struct MonitorDescriptor { > + uint16_t Flag0; > + uint8_t Flag1; > + uint8_t DataTypeTag; > + uint8_t Flag2; > + uint8_t DescriptorData[13]; > +}__attribute__((__packed__)); > + > +union DTD_MD { > + struct DetailedTimingDescriptor dtd; > + struct MonitorDescriptor md; > +}; > + > +#define EDID_STI_DescriptorUnused 0x0101 > +#define EDID_STI_AspectRatio_16_10 0 > +#define EDID_STI_AspectRatio_4_3 1 > +#define EDID_STI_AspectRatio_5_4 2 > +#define EDID_STI_AspectRatio_16_9 3 > +struct StandardTimingIdentification { > + uint8_t HorizontalActivePixels; > + uint8_t ImageAspectRatio : 2; > + uint8_t RefreshRate : 6; > +}__attribute__((__packed__)); > + > +struct VID_Analog { > + uint8_t SerationOnVerticalSync : 1; > + uint8_t SyncSignalOnGreen : 1; > + uint8_t SyncSignalOnHorizontal : 1; > + uint8_t SeparateSyncHandVSignals: 1; > + uint8_t VideoSetupBlank : 1; > + uint8_t SignalLevelStandard : 2; > + uint8_t DigitalSignalLevel : 1; /* Analog = 0, Digital = 1*/ > +}__attribute__((__packed__)); > + > +struct VID_Digital { > + uint8_t DigitalVideoStandardSupp: 4; > + uint8_t ColorBitDepth : 3; > + uint8_t DigitalSignalLevel : 1; > +}__attribute__((__packed__)); > + > +/* Color Bit Depths */ > +#define CBD_undef 0x0 > +#define CBD_6bPerPrimaryColor 0x1 > +#define CBD_8bPerPrimaryColor 0x2 > +#define CBD_10bPerPrimaryColor 0x3 > +#define CBD_12bPerPrimaryColor 0x4 > +#define CBD_14bPerPrimaryColor 0x5 > +#define CBD_16bPerPrimaryColor 0x6 > +#define CBD_reserved 0x7 > + > +/* Digital Video Standard Supported */ > +#define DVS_undef 0x0 > +#define DVS_DVI 0x1 > +#define DVS_HDMI-a 0x2 > +#define DVS_HDMI-b 0x3 > +#define DVS_MDDI 0x4 > +#define DVS_DiplayPort 0x5 > + > +union VideoInputDefinition { > + struct VID_Analog analog; > + struct VID_Digital digital; > +}; > + > +struct edid1{ > + uint8_t Header[8]; > +/* Vendor Product Identification */ > + uint16_t IDManufacturerName; > + uint16_t IDProductCode; > + uint32_t IDSerialNumber; > + uint8_t WeekofManufacture; > + uint8_t YearofManufacture; > +/* EDID Structure Version Revision Level */ > + uint8_t Version; > + uint8_t Revision; > +/* Basic Display Parameters Features */ > + /* Video Input Definition */ > + union VideoInputDefinition vid; > + uint8_t MaxHorizontalImageSize; > + uint8_t MaxVerticalImageSize; > + uint8_t DisplayTransferCharacteristic; > + /* Feature Support */ > + uint8_t Feature_GTFSupported : 1; > + uint8_t Feature_PreferredTimingMode : 1; > + uint8_t Feature_StandardDefaultColorSpace : 1; > + uint8_t Feature_DisplayType : 2; > + /* Refer to VESA DPMS Specification */ > + uint8_t Feature_ActiveOff : 1; > + uint8_t Feature_Suspend : 1; > + uint8_t Feature_StandBy : 1; > +/* Color Characteristics */ > + uint8_t GreenYLow : 2; > + uint8_t GreenXLow : 2; > + uint8_t RedYLow : 2; > + uint8_t RedXLow : 2; > + uint8_t WhiteYLow : 2; > + uint8_t WhiteXLow : 2; > + uint8_t BlueYLow : 2; > + uint8_t BlueXLow : 2; > + uint8_t RedXHigh; > + uint8_t RedYHigh; > + uint8_t GreenXHigh; > + uint8_t GreenYHigh; > + uint8_t BlueXHigh; > + uint8_t BlueYHigh; > + uint8_t WhiteXHigh; > + uint8_t WhiteYHigh; > +/* Established Timings I */ > + uint8_t EST_800x600_60Hz : 1; > + uint8_t EST_800x600_56Hz : 1; > + uint8_t EST_640x480_75Hz : 1; > + uint8_t EST_640x480_72Hz : 1; > + uint8_t EST_640x480_67Hz : 1; > + uint8_t EST_640x480_60Hz : 1; > + uint8_t EST_720x400_88Hz : 1; > + uint8_t EST_720x400_70Hz : 1; > +/* Established Timings II */ > + uint8_t EST_1280x1024_75Hz : 1; > + uint8_t EST_1024x768_75Hz : 1; > + uint8_t EST_1024x768_70Hz : 1; > + uint8_t EST_1024x768_60Hz : 1; > + uint8_t EST_1024x768_87Hz : 1; > + uint8_t EST_832x624_75Hz : 1; > + uint8_t EST_800x600_75Hz : 1; > + uint8_t EST_800x600_72Hz : 1; > +/* Manufacturer's Timings */ > + uint8_t EST_Reserved : 7; > + uint8_t EST_1152x870_75Hz : 1; > +/* Standard Timing Identification */ > + struct StandardTimingIdentification STI[8]; > +/* Detailed Timing Descriptions / Monitor Descriptions */ > + union DTD_MD dtd_md[4]; > + uint8_t ExtensionFlag; > + uint8_t Checksum; > +}__attribute__((__packed__)); > + > +/**** structs and defines for EDIDv2 ****/ > + > +struct EDID2_AnalogInterfaceDataFormatDescription{ > + uint8_t SyncInputsSupported0 : 1; > + uint8_t SyncInputsSupported1 : 1; > + uint8_t SyncInputsSupported2 : 1; > + uint8_t SyncInputsSupported3 : 1; > + uint8_t Setup : 1; > + uint8_t SignalLevelStandard : 2; > + uint8_t Reserved0 : 1; > + > + uint8_t Reserved1 : 7; > + uint8_t PixelClockSupported : 1; > + uint8_t Reserved2; > + uint8_t Reserved3; > +}__attribute__((__packed__)); > + > +struct EDID2_DigitalInterfaceDataFormatDescription{ > + uint8_t ChannelSpeedExponent : 4; > + uint8_t NumberOfReceiverUnits : 2; > + uint8_t EdgeOfShiftClockUsed : 1; > + uint8_t DisplayEnablePolarity : 1; > + > + uint8_t MinimumChannelSpeed; > + uint8_t MaximumChannelSpeed; > + uint8_t DigitalInterfaceDataFormat; > +}__attribute__((__packed__)); > + > +union EDID2_InterfaceDataFormatDescription{ > + struct EDID2_AnalogInterfaceDataFormatDescription analog; > + struct EDID2_DigitalInterfaceDataFormatDescription digital; > +}; > + > +struct edid2{ > +/* EDID Structure Version/Revision */ > + uint8_t Revision : 4; > + uint8_t Version : 4; > +/* Vendor / Product Identification */ > + uint16_t IDManufacturerName; > + uint16_t IDProductCode; > + uint8_t WeekOfManufacture; > + uint16_t YearOfManufacture; > +/* Manufacturer/Product Name String */ > + char ManufacturerProductIDstring[32]; > +/* Serial Number String */ > + char SerialNumberString[16]; > +/* Unused (Reserved) */ > + uint8_t Unused0[8]; > +/* Display Interface Parameters */ > + /* Physical Connector Type */ > + uint8_t PhysicalInterfaceSecondary : 4; /* see Physical Connector Types > */ > + uint8_t PhysicalInterfaceDefault : 4; /* see Physical Connector Types > */ > + uint8_t VideoInterfaceTypeSecondary : 4; > + uint8_t VideoInterfaceTypeDefault : 4; > + union EDID2_InterfaceDataFormatDescription IDFDefault; > + union EDID2_InterfaceDataFormatDescription IDFSecondary; > + /* Interface Color Luminance Encoding */ > + uint8_t CLE_ColorencodingSecondary : 4; > + uint8_t CLE_ColorencodingDefault : 4; > + /* SC - sub-channel; 0 - red, 1 - green, 2 - blue */ > + uint8_t CLE_supportedBitDepthSC1Default : 4; > + uint8_t CLE_supportedBitDepthSC0Default : 4; > + uint8_t CLE_supportedBitDepthSC3Default : 4; > + uint8_t CLE_supportedBitDepthSC2Default : 4; > + uint8_t CLE_supportedBitDepthSC1Secondary : 4; > + uint8_t CLE_supportedBitDepthSC0Secondary : 4; > + uint8_t CLE_supportedBitDepthSC3Secondary : 4; > + uint8_t CLE_supportedBitDepthSC2Secondary : 4; > +/* Display Device Description */ > + uint8_t DisplayTechnologySubtype : 4; > + uint8_t DisplayTechnologyType : 4; > + /* Major Display Characteristics */ > + uint8_t MDC_PhysicalImplementation : 2; > + uint8_t MDC_DisplayBackground : 1; > + uint8_t MDC_ScanOrientation : 2; > + uint8_t MDC_Conditionalupdate : 1; > + uint8_t MDC_SelectableDisplayChromacity : 1; > + uint8_t MDC_Color : 1; > + /* Features */ > + uint8_t Features_Reserved0 : 1; > + uint8_t Features_StereoSupport : 3; > + uint8_t Features_Off : 1; > + uint8_t Features_ActiveOff : 1; > + uint8_t Features_Suspend : 1; > + uint8_t Features_StandBy : 1; > + > + uint8_t Features_VideoInput : 2; > + uint8_t Features_AudioOutputInterface : 2; > + uint8_t Features_AudioOutput : 1; > + uint8_t Features_AudioInputInterface : 2; > + uint8_t Features_AudioInput : 1; > + > + uint8_t Features_Reserved1 : 3; > + uint8_t Features_AdjustableOrientation : 1; > + uint8_t Features_Colorimeter : 1; > + uint8_t Features_LuminanceProbe : 1; > + uint8_t Features_LightPen : 1; > + uint8_t Features_TouchScreen : 1; > +/* Display Response Time; Seconds - Range 0-15 * 10^(-n), n=timeexp */ > + uint8_t DRT_RiseTimeResponseInSeconds : 4; > + uint8_t DRT_RiseTimeExponent : 4; > + uint8_t DRT_FallTimeResponseInSeconds : 4; > + uint8_t DRT_FallTimeExponent : 4; > +/* Color Luminance Description */ > + uint8_t DisplayTransferCharacteristic_WhiteGamma; > + uint8_t DisplayTransferCharacteristic_Color0Gamma; > + uint8_t DisplayTransferCharacteristic_Color1Gamma; > + uint8_t DisplayTransferCharacteristic_Color2Gamma; > + uint16_t MaximumLuminanceWhite; > + uint8_t LuminanceFlag_OffsetSignBit : 1; > + uint8_t LuminanceFlags_Reserved : 5; > + uint8_t LuminanceFlag_AdjustableGamma : 1; > + uint8_t LuminanceFlag_StandardRGBmodel : 1; > + uint8_t LuminanceOffset; > + /* Chromacity and Default White Point Coordinates */ > + uint8_t ColorCharacteristicsGreenYLow : 2; > + uint8_t ColorCharacteristicsGreenXLow : 2; > + uint8_t ColorCharacteristicsRedYLow : 2; > + uint8_t ColorCharacteristicsRedXLow : 2; > + uint8_t ColorCharacteristicsWhiteYLow : 2; > + uint8_t ColorCharacteristicsWhiteXLow : 2; > + uint8_t ColorCharacteristicsBlueYLow : 2; > + uint8_t ColorCharacteristicsBlueXLow : 2; > + uint8_t ColorCharacteristicsRedXHigh; > + uint8_t ColorCharacteristicsRedYHigh; > + uint8_t ColorCharacteristicsGreenXHigh; > + uint8_t ColorCharacteristicsGreenYHigh; > + uint8_t ColorCharacteristicsBlueXHigh; > + uint8_t ColorCharacteristicsBlueYHigh; > + uint8_t ColorCharacteristicsWhiteXHigh; > + uint8_t ColorCharacteristicsWhiteYHigh; > + /* Additional White Points And Gamma */ > + struct ColorPointData cpd[2]; > +/* Display Spatial Description */ > + uint16_t MaxHorizontalImageSize; > + uint16_t MaxVerticalImageSize; > + uint16_t MaxHorizontalAddressibility; > + uint16_t MaxVerticalAddressibility; > + uint8_t HorizontalPixelPitch; > + uint8_t VerticalPixelPitch; > +/* Unused (Reserved) */ > + uint8_t Unused1; > +/* GTF Support Information */ > + uint8_t GTFSupportInformationSecond : 4; > + uint8_t GTFSupportInformation : 4; > +/* Map Of Timing Information */ > + uint8_t MTI_NumberOfDetailedRangeLimitsListed : 2; > + uint8_t MTI_NumberOfFrequencyRangesListed : 3; > + uint8_t MTI_LuminanceTableProvided : 1; > + uint8_t MTI_PreferredTimingMode : 1; > + uint8_t MTI_ExtensionFlag : 1; > + uint8_t MTI_NumberOfDetailedTimingDescriptions : 3; > + uint8_t MTI_NumberOf4byteTimingCodesListed : 5; > +/* 80h Luminance Table Timing Descriptions */ > + uint8_t LuminanceTableTimingDescriptions[0x7F]; > +/* x*A Luminance Table */ > +/* 8*B Range Limits */ > +/* 27*C 27-Byte Detailed Range Limits */ > +/* 4*D 4-Byte Timing Codes */ > +/* 18*E 18-Byte Detailed Timing Descriptions */ > +/* zeros up to FEh */ > + uint8_t Checksum; > +}__attribute__((__packed__)); > + > +/* Luminance Table */ > +struct LuminanceTable { > + uint8_t NumberOfLuminanceEntries : 5; /* n */ > + uint8_t Reserved : 2; > + uint8_t SeparateSubChannels : 1; /* s */ > + uint8_t LuminanceValues; /* if s==0 there are n else 3*n bytes here */ > +}__attribute__((__packed__)); > +/* Range Limits */ > +struct DisplayTimingRangeLimits { > + uint8_t MinFrameFieldRateInHzHigh; > + uint8_t MaxFrameFieldRateInHzHigh; > + uint8_t MinLineRateInkHzHigh; > + uint8_t MaxLineRateInkHzHigh; > + uint8_t MaxLineRateInkHzLow : 2; > + uint8_t MinLineRateInkHzLow : 2; > + uint8_t MaxFrameFieldRateInHzLow : 2; > + uint8_t MinFrameFieldRateInHzLow : 2; > + uint8_t MinPixelRateInMHzLow; > + uint8_t MaxPixelRateInMHzLow; > + uint8_t MaxPixelRateInMHzHigh : 4; > + uint8_t MinPixelRateInMHzHigh : 4; > +}__attribute__((__packed__)); > +/* 27-Byte Detailed Range Limits */ > +struct DetailedTimingRangeFormat27B { > + uint16_t MinPixelClock_div10000; > + uint8_t MinHorizontalBlankingLow; > + uint8_t MinVerticalBlankingLow; > + uint8_t MinVerticalBlankingHigh : 4; > + uint8_t MinHorizontalBlankingHigh : 4; > + uint8_t MinHorizontalSyncOffsetLow; > + uint8_t MinHorizontalSyncPulseWidthLow; > + uint8_t MinVerticalSyncPulseWidthLow : 4; > + uint8_t MinVerticalSyncOffsetLow : 4; > + uint8_t MinVerticalSyncPulseWidthHigh : 2; > + uint8_t MinVerticalSyncOffsetHigh : 2; > + uint8_t MinHorizontalSyncPulseWidthHigh : 2; > + uint8_t MinHorizontalSyncOffsetHigh : 2; > + uint16_t MaxPixelClock_div10000; > + uint8_t MaxHorizontalBlankingLow; > + uint8_t MaxVerticalBlankingLow; > + uint8_t MaxVerticalBlankingHigh : 4; > + uint8_t MaxHorizontalBlankingHigh : 4; > + uint8_t MaxHorizontalSyncOffsetLow; > + uint8_t MaxHorizontalSyncPulseWidthLow; > + uint8_t MaxVerticalSyncPulseWidthLow : 4; > + uint8_t MaxVerticalSyncOffsetLow : 4; > + uint8_t MaxVerticalSyncPulseWidthHigh : 2; > + uint8_t MaxVerticalSyncOffsetHigh : 2; > + uint8_t MaxHorizontalSyncPulseWidthHigh : 2; > + uint8_t MaxHorizontalSyncOffsetHigh : 2; > + uint8_t HorizontalImageSizeLow; > + uint8_t VerticalImageSizeLow; > + uint8_t VerticalImageSizeHigh : 4; > + uint8_t HorizontalImageSizeHigh : 4; > + uint8_t HorizontalActiveLow; > + uint8_t VerticalActiveLow; > + uint8_t VerticalActiveHigh : 4; > + uint8_t HorizontalActiveHigh : 4; > + uint8_t HorizontalBorder; > + uint8_t VerticalBorder; > + uint8_t Flags_Set0 : 1; > + /* Next four bits are specified for digital interfaces. > + Meaning for analog interfaces shall be found > + in the document mentioned above. */ > + uint8_t Flags_LPPolarity : 1; > + uint8_t Flags_FLMPolarity : 1; > + uint8_t Flags_Reserved : 1; > + uint8_t Flags_ShiftClockUse : 1; > + uint8_t Flags_Set1 : 2; > + uint8_t Flags_Interlaced : 1; > +}__attribute__((__packed__)); > +/* 4-Byte Timing Codes */ > +struct TimingCodeFormat4B { > + uint8_t ActivePixelsPerLine; > + uint8_t Reserved : 1; > + uint8_t SHFTCLKedgesUsed : 1; > + uint8_t FLMPolarity : 1; > + uint8_t LPPolarity : 1; > + uint8_t Portrait : 1; > + uint8_t Stereo : 1; > + uint8_t InterlacedTiming : 1; > + uint8_t ReducedBlanking : 1; > + uint8_t FormatAspectRatio; > + uint8_t RefreshRate; > +}__attribute__((__packed__)); > +/* 18-Byte Detailed Timing Descriptions */ > + /* see struct DetailedTimingDescriptor */ > + > +/* Physical Connector Types (Default/SecondaryPhysicalInterface) */ > +#define EDID2_PCT_None 0x0 > +#define EDID2_PCT_BNC 0x1 > +#define EDID2_PCT_15pinVGA 0x2 > +#define EDID2_PCT_13w3 0x3 > +#define EDID2_PCT_VESAEVC 0x4 > +#define EDID2_PCT_VESAPDD 0x5 > +#define EDID2_PCT_Microribbon 0x6 > +#define EDID2_PCT_IEEE1394 0x7 > +#define EDID2_PCT_VESAFPDI2 0x8 > +/* Reserved 0x9-0xE */ > +#define EDID2_PCT_Nonstandard 0xF > + > +/* Video Interface Type */ > +#define EDID2_VIT_None 0x0 > +#define EDID2_VIT_Analog 0x1 > +#define EDID2_VIT_Analogwsampledpixelclock 0x2 > + /* Transition Minimized Differential Signaling */ > +#define EDID2_VIT_TMDS 0x3 > +#define EDID2_VIT_IEEE1394_1995 0x4 > +#define EDID2_VIT_LVDS 0x5 > +#define EDID2_VIT_Parallel 0x6 > +/* Reserved 0x7-0xF */ > + > +/* digital interface data format */ > +/* ... */ > +#define EDID2_didf_RGB_STN-DD_8BitOver8Bit 0x15 > +#define EDID2_didf_RGB_STN-DD_12BitOver12Bit 0x19 > +/* ... */ > +#define EDID2_didf_MSBAlignedRGBTFT24Bit 0x24 > +/* ... */ > + > +/* Color/Luminance Encoding Description */ > + /* nibbles of byte 0 - color encodings */ > +#define EDID2_CLE_CE_Monochrome 0x0 > +#define EDID2_CLE_CE_RGBadd 0x1 > +#define EDID2_CLE_CE_CMYsub 0x2 > +#define EDID2_CLE_CE_CMYKsub 0x3 > +#define EDID2_CLE_CE_YC_NTSC 0x4 > +#define EDID2_CLE_CE_YC_PAL 0x5 > +#define EDID2_CLE_CE_YC_SECAM 0x6 > +#define EDID2_CLE_CE_YIQ_NTSC 0x7 > +#define EDID2_CLE_CE_YIQ_PAL 0x8 > +#define EDID2_CLE_CE_YIQ_SECAM 0x9 > +#define EDID2_CLE_CE_YCrCb 0xA > +#define EDID2_CLE_CE_YPrPb 0xB > +#define EDID2_CLE_CE_XYZ 0xC > +#define EDID2_CLE_CE_CIELuv 0xD > +#define EDID2_CLE_CE_CIELab 0xE > +#define EDID2_CLE_CE_Digital_ATSC 0xF > + > +/* Display Device Description; T-type, ST-subtype */ > +#define EDID2_DDD_T_CRT 0x0 /* Cathode Ray Tube */ > +#define EDID2_DDD_ST_CRT_Monochrome 0x0 > +#define EDID2_DDD_ST_CRT_ShadowmaskColor 0x1 > +#define EDID2_DDD_ST_CRT_BeamIndexColor 0x2 > +#define EDID2_DDD_ST_CRT_BeamPenetrationColor 0x3 > + > +#define EDID2_DDD_T_LCD 0x1 /* Liquid Crystal Display */ > +#define EDID2_DDD_ST_LCD_STN 0x0 > +#define EDID2_DDD_ST_LCD_DSTN 0x1 > +#define EDID2_DDD_ST_LCD_FLCD 0x2 > +#define EDID2_DDD_ST_LCD_TFTconv 0x3 > +#define EDID2_DDD_ST_LCD_TFTinplaneswtch 0x4 > +#define EDID2_DDD_ST_LCD_PDLCD 0x5 > +#define EDID2_DDD_ST_LCD_PSCLCD 0x6 > +#define EDID2_DDD_ST_LCD_PALCD 0x7 > + > +#define EDID2_DDD_T_EL 0x2 /* Electroluminiscent Displ */ > +#define EDID2_DDD_ST_EL_ACThin 0x0 > +#define EDID2_DDD_ST_EL_ACThick 0x1 > +#define EDID2_DDD_ST_EL_DCThin 0x2 > +#define EDID2_DDD_ST_EL_DCThick 0x3 > + > +#define EDID2_DDD_T_PDP 0x3 /* Plasma Display Panel */ > +#define EDID2_DDD_ST_PDP_AC 0x0 > +#define EDID2_DDD_ST_PDP_DC 0x1 > + > +#define EDID2_DDD_T_FED 0x4 /* Field Emission Displays */ > +#define EDID2_DDD_ST_FED_TBD 0x0 > + > +#define EDID2_DDD_T_LED 0x5 /* Light Emitting Diode */ > +#define EDID2_DDD_ST_LED_TBD 0x0 > + > +#define EDID2_DDD_T_IRD 0x6 /* Integrated Reflective Display */ > +#define EDID2_DDD_ST_IRD_1Chip 0x0 > +#define EDID2_DDD_ST_IRD_2Chip 0x1 > +#define EDID2_DDD_ST_IRD_3Chip 0x2 > + > + /* Types 0x7-0xF Reserved */ > + > +/* MajorDisplayCharacteristics */ > +#define EDID2_MDC_C_Color 1 > +#define EDID2_MDC_C_Mono 0 > +#define EDID2_MDC_SO_notscanned 0x0 > +#define EDID2_MDC_SO_fastLRslowTB 0x1 > +#define EDID2_MDC_SO_fastTBslowLR 0x2 > +#define EDID2_MDC_SO_fastTBslowRL 0x3 > +#define EDID2_MDC_DB_NonTransp 0 > +#define EDID2_MDC_DB_Transparent 1 > +#define EDID2_MDC_PI_Large 0x0 > +#define EDID2_MDC_PI_Desktop 0x1 > +#define EDID2_MDC_PI_Eyepiece 0x2 > + > +/* FeaturesSupport */ > + /* byte 0 - refer to VESA DPMS specification */ > + /* Stereo Support */ > +#define EDID2_FS_SS_nodirectstereo 0x0 > +#define EDID2_FS_SS_fieldseqstereo 0x1 > +#define EDID2_FS_SS_directviewcolumnilv 0x2 > +#define EDID2_FS_SS_directviewlineilv 0x3 > + /* byte 1 */ > + /* VideoInputValues */ > +#define EDID2_FX_VI_None 0x0 > +#define EDID2_FX_VI_AnalogYCconnEVC 0x1 > +#define EDID2_FX_VI_USBCam 0x2 > +#define EDID2_FX_VI_IEEE1394Cam 0x3 > + /* AudioOutputInterfaceValues */ > +#define EDID2_FS_AOI_None 0x0 > +#define EDID2_FS_AOI_Analog 0x1 > +#define EDID2_FS_AOI_USB 0x2 > +#define EDID2_FS_AOI_IEEE1394 0x3 > + /* Audio Input Interface Values */ > +#define EDID2_FS_AII_None 0x0 > +#define EDID2_FS_AII_Analog 0x1 > +#define EDID2_FS_AII_USB 0x2 > +#define EDID2_FS_AII_IEEE1394 0x3 > + > +/* GTFSupportInformation values */ > +#define EDID2_GTFSI_nosupport 0x0 > +#define EDID2_GTFSI_stdCRTparams 0x1 > +#define EDID2_GTFSI_defaultTBD 0x2 > +#define EDID2_GTFSI_custom 0xF > + > +union edid { > + struct edid1 edid1; > + struct edid2 edid2; > +}; > + > +#ifdef __cplusplus > +} > +#endif /* __cplusplus */ > + > +#endif /* ASM */ > + > +#endif /* _VBE_H */ > diff --git a/c/src/lib/libbsp/i386/pc386/include/vbe3.h > b/c/src/lib/libbsp/i386/pc386/include/vbe3.h > new file mode 100644 > index 0000000..152d552 > --- /dev/null > +++ b/c/src/lib/libbsp/i386/pc386/include/vbe3.h > @@ -0,0 +1,461 @@ > +/** > + * @file vbe3.h > + * > + * @ingroup i386_pc386 > + * > + * @brief VESA Bios Extension definitions. > + */ > + > +/* > + * vbe3.h - This file contains definitions for constants related to VBE. > + * More information can be found at > + * <http://www.vesa.org/vesa-standards/free-standards/> > + * VESA public standards may be found at > + * <http://www.vesa.org/wp-content/uploads/2010/12/thankspublic.htm> > + * > + * Copyright (C) 2014 Jan Doležal (dolez...@fel.cvut.cz) > + * CTU in Prague. > + * > + * The license and distribution terms for this file may be > + * found in the file LICENSE in this distribution or at > + * http://www.rtems.org/license/LICENSE. > + */ > + > +#ifndef _VBE_H > +#define _VBE_H > + > +#ifndef ASM /* ASM */ > + > +#include <stdint.h> > + > +#ifdef __cplusplus > +extern "C" { > +#endif /* __cplusplus */ > + > + > +/* VESA BIOS EXTENSION (VBE) Core functions Standard > + Version: 3.0 Date: September 16, 1998 */ > + > +/* VBE RETURN STATUS */ > +/* AL == 4Fh: Function is supported */ > +/* AL != 4Fh: Function is not supported */ > +#define VBE_functionSupported 0x4F > +/* AH == 00h: Function call successful */ > +#define VBE_callSuccessful 0x00 > +/* AH == 01h: Function call failed */ > +#define VBE_callFailed 0x01 > +/* AH == 02h: Function is not supported in the current hardware > configuration */ > +#define VBE_notSupportedInCurHWConf 0x02 > +/* AH == 03h: Function call invalid in current video mode */ > +#define VBE_callInvalid 0x03 > + > +/* VBE Mode Numbers */ > +/* D0-D8 = Mode number */ > +#define VBE_modeNumberMask 0x01FF > +#define VBE_modeNumberShift 0x00 > +/* If D8 == 0, this is not a VESA defined VBE mode */ > +#define VBE_VESAmodeMask 0x0100 > +/* If D8 == 1, this is a VESA defined VBE mode */ > +/* D9-D12 = Reserved by VESA for future expansion (= 0) */ > +#define VBE_VESAmodeShift 0x08 > +/* If D11 == 0, Use current BIOS default refresh rate */ > +#define VBE_refreshRateCtrlMask 0x0800 > +/* If D11 == 1, Use user specified CRTC values for refresh rate */ > +/* D12-13 = Reserved for VBE/AF (must be 0) */ > +#define VBE_refreshRateCtrlShift 0x0B > +/* If D14 == 0, Use Banked/Windowed Frame Buffer */ > +#define VBE_linearFlatFrameBufMask 0x4000 > +/* If D14 == 1, Use Linear/Flat Frame Buffer */ > +#define VBE_linearFlatFrameBufShift 0x0E > +/* If D15 == 0, Clear display memory */ > +#define VBE_preserveDispMemMask 0x8000 > +/* If D15 == 1, Preserve display memory */ > +#define VBE_preserveDispMemShift 0x0F > + > +/* Graphics modes */ > +/* 15-bit mode, Resolution: 640x400, Colors: 256 */ > +#define VBE_R640x400C256 0x100 > +/* 15-bit mode, Resolution: 640x480, Colors: 256 */ > +#define VBE_R640x480C256 0x101 > +/* 15-bit mode, Resolution: 800x600, Colors: 16 */ > +#define VBE_R800x600C16 0x102 > +/* 7-bit mode, Resolution: 800x600, Colors: 16 */ > +#define VBE_b7R800x600C16 0x6A > +/* 15-bit mode, Resolution: 800x600, Colors: 256 */ > +#define VBE_R800x600C256 0x103 > +/* 15-bit mode, Resolution: 1024x768, Colors: 16 */ > +#define VBE_R1024x768C16 0x104 > +/* 15-bit mode, Resolution: 1024x768, Colors: 256 */ > +#define VBE_R1024x768C256 0x105 > +/* 15-bit mode, Resolution: 1280x1024, Colors: 16 */ > +#define VBE_R1280x1024C16 0x106 > +/* 15-bit mode, Resolution: 1280x1024, Colors: 256 */ > +#define VBE_R1280x1024C256 0x107 > +/* 15-bit mode, Resolution: 320x200, Colors: 32K (1:5:5:5) */ > +#define VBE_R320x200C32K 0x10D > +/* 15-bit mode, Resolution: 320x200, Colors: 64K (5:6:5) */ > +#define VBE_R320x200C64K 0x10E > +/* 15-bit mode, Resolution: 320x200, Colors: 16.8M (8:8:8) */ > +#define VBE_R320x200C17M 0x10F > +/* 15-bit mode, Resolution: 640x480, Colors: 32K (1:5:5:5) */ > +#define VBE_R640x480C32K 0x110 > +/* 15-bit mode, Resolution: 640x480, Colors: 64K (5:6:5) */ > +#define VBE_R640x480C64K 0x111 > +/* 15-bit mode, Resolution: 640x480, Colors: 16.8M (8:8:8) */ > +#define VBE_R640x480C17M 0x112 > +/* 15-bit mode, Resolution: 800x600, Colors: 32K (1:5:5:5) */ > +#define VBE_R800x600C32K 0x113 > +/* 15-bit mode, Resolution: 800x600, Colors: 64K (5:6:5) */ > +#define VBE_R800x600C64K 0x114 > +/* 15-bit mode, Resolution: 800x600, Colors: 16.8M (8:8:8) */ > +#define VBE_R800x600C17M 0x115 > +/* 15-bit mode, Resolution: 1024x768, Colors: 32K (1:5:5:5) */ > +#define VBE_R1024x768C32K 0x116 > +/* 15-bit mode, Resolution: 1024x768, Colors: 64K (5:6:5) */ > +#define VBE_R1024x768C64K 0x117 > +/* 15-bit mode, Resolution: 1024x768, Colors: 16.8M (8:8:8) */ > +#define VBE_R1024x768C17M 0x118 > +/* 15-bit mode, Resolution: 1280x1024, Colors: 32K (1:5:5:5) */ > +#define VBE_R1280x1024C32K 0x119 > +/* 15-bit mode, Resolution: 1280x1024, Colors: 64K (5:6:5) */ > +#define VBE_R1280x1024C64K 0x11A > +/* 15-bit mode, Resolution: 1280x1024, Colors: 16.8M (8:8:8) */ > +#define VBE_R1280x1024C17M 0x11B > +#define VBE_SpecialMode 0x81FF > + > +/* Text modes */ > +#define VBE_C80R60 0x108 /* 15-bit mode, Columns: 80, Rows: 60 > */ > +#define VBE_C132R25 0x109 /* 15-bit mode, Columns: 132, Rows: 25 > */ > +#define VBE_C132R43 0x10A /* 15-bit mode, Columns: 132, Rows: 43 > */ > +#define VBE_C132R50 0x10B /* 15-bit mode, Columns: 132, Rows: 50 > */ > +#define VBE_C132R60 0x10C /* 15-bit mode, Columns: 132, Rows: 60 > */ > + > +/* VBE function numbers - passed in AX register */ > +#define VBE_RetVBEConInf 0x4F00 /* Return VBE Controller Information */ > +#define VBE_RetVBEModInf 0x4F01 /* Return VBE Mode Information */ > +#define VBE_SetVBEMod 0x4F02 /* Set VBE Mode */ > +#define VBE_RetCurVBEMod 0x4F03 /* Return Current VBE Mode */ > +#define VBE_SavResSta 0x4F04 /* Save/Restore State */ > +#define VBE_DisWinCon 0x4F05 /* Display Window Control */ > +#define VBE_SetGetLogScaLinLen 0x4F06 /* Set/Get Logical Scan Line Length */ > +#define VBE_SetGetDisSta 0x4F07 /* Set/Get Display Start */ > +#define VBE_SetGetDACPalFor 0x4F08 /* Set/Get DAC Palette Format */ > +#define VBE_SetGetPalDat 0x4F09 /* Set/Get Palette Data */ > +#define VBE_RetVBEProModInt 0x4F0A /* Return VBE Protected Mode Interface > */ > +#define VBE_GetSetpixclo 0x4F0B /* Get/Set pixel clock */ > +#define VBE_PowManExt 0x4F10 /* Power Management Extensions (PM) */ > +#define VBE_FlaPanIntExt 0x4F11 /* Flat Panel Interface Extensions > (FP) */ > +#define VBE_AudIntExt 0x4F13 /* Audio Interface Extensions (AI) */ > +#define VBE_OEMExt 0x4F14 /* OEM Extensions */ > +#define VBE_DisDatCha 0x4F15 /* Display Data Channel (DDC), > + Serial Control Interface (SCI) */ > + > +/* VBE subfunction numbers - passed in BL register */ > +#define VBE_RetVBESupSpeInf 0x00 /* Return VBE Supplemental > + Specification Information */ > +/* *** Structures *** */ > +struct VBE_FarPtr { > + uint16_t offset; > + uint16_t selector; > +} __attribute__((__packed__)) ; > + > +struct VBE_PMInfoBlock { > + uint8_t Signature[4]; /* PM Info Block Signature */ > + uint16_t EntryPoint; /* Offset of PM entry point within BIOS */ > + uint16_t PMInitialize; /* Offset of PM initialization entry point */ > + uint16_t BIOSDataSel; /* Selector to BIOS data area emulation > block */ > + uint16_t A0000Sel; /* Selector to access A0000h physical mem */ > + uint16_t B0000Sel; /* Selector to access B0000h physical mem */ > + uint16_t B8000Sel; /* Selector to access B8000h physical mem */ > + uint16_t CodeSegSel; /* Selector to access code segment as data */ > + uint8_t InProtectMode; /* Set to 1 when in protected mode */ > + uint8_t Checksum; /* Checksum byte for structure */ > +} __attribute__((__packed__)) ; > + > +/* General VBE signature */ > +#define VBE_SIGNATURE "VESA" > +/* Signature for VBE 2.0 and higher */ > +#define VBE20plus_SIGNATURE "VBE2" > +/* for STUB see VBE CORE FUNCTIONS VERSION 3.0 - Appendix 1 */ > +#define VBE_END_OF_VideoModeList 0xFFFF > +#define VBE_STUB_VideoModeList 0xFFFF > +struct VBE_VbeInfoBlock { > + uint8_t VbeSignature[4]; /* VBE Signature */ > + uint16_t VbeVersion; /* VBE Version */ > + uint8_t *OemStringPtr; /* VbeFarPtr to OEM String */ > + uint8_t Capabilities[4]; /* Capabilities of graphics controller */ > + uint32_t *VideoModePtr; /* VbeFarPtr to VideoModeList */ > + uint16_t TotalMemory; /* Number of 64kb memory blocks */ > + /* Added for VBE 2.0+ */ > + uint16_t OemSoftwareRev; /* VBE implementation Software revision */ > + uint8_t *OemVendorNamePtr; /* VbeFarPtr to Vendor Name String */ > + uint8_t *OemProductNamePtr; /* VbeFarPtr to Product Name String */ > + uint8_t *OemProductRevPtr; /* VbeFarPtr to Product Revision String */ > + uint8_t Reserved[222]; /* Reserved for VBE implementation scratch > */ > + /* area */ > + uint8_t OemData[256]; /* Data Area for OEM Strings */ > +} __attribute__((__packed__)) ; > + > +struct VBE_ModeInfoBlock { > + /* Mandatory information for all VBE revisions */ > + uint16_t ModeAttributes; /* mode attributes */ > + uint8_t WinAAttributes; /* window A attributes */ > + uint8_t WinBAttributes; /* window B attributes */ > + uint16_t WinGranularity; /* window granularity */ > + uint16_t WinSize; /* window size */ > + uint16_t WinASegment; /* window A start segment */ > + uint16_t WinBSegment; /* window B start segment */ > + uint32_t *WinFuncPtr; /* real mode pointer to window function > */ > + uint16_t BytesPerScanLine; /* bytes per scan line */ > + /* Mandatory information for VBE 1.2 and above */ > + uint16_t XResolution; /* horizontal resolution in px or chars > */ > + uint16_t YResolution; /* vertical resolution in px or chars */ > + uint8_t XCharSize; /* character cell width in pixels */ > + uint8_t YCharSize; /* character cell height in pixels */ > + uint8_t NumberOfPlanes; /* number of memory planes */ > + uint8_t BitsPerPixel; /* bits per pixel */ > + uint8_t NumberOfBanks; /* number of banks */ > + uint8_t MemoryModel; /* memory model type */ > + uint8_t BankSize; /* bank size in KB */ > + uint8_t NumberOfImagePages; /* number of images */ > + uint8_t Reserved0; /* reserved for page function */ > + /* Direct Color fields (required for direct/6 and YUV/7 memory models) > */ > + uint8_t RedMaskSize; /* size of direct color red mask in > bits */ > + uint8_t RedFieldPosition; /* bit position of lsb of red mask */ > + uint8_t GreenMaskSize; /* size of direct color green mask in b > */ > + uint8_t GreenFieldPosition; /* bit position of lsb of green mask */ > + uint8_t BlueMaskSize; /* size of direct color blue mask in b > */ > + uint8_t BlueFieldPosition; /* bit position of lsb of blue mask */ > + uint8_t RsvdMaskSize; /* size of direct color reserved mask */ > + uint8_t RsvdFieldPosition; /* bit position of lsb of reserved mask > */ > + uint8_t DirectColorModeInfo; /* direct color mode attributes */ > + /* Mandatory information for VBE 2.0 and above */ > + uint32_t *PhysBasePtr; /* physical address for > + flat memory frame buffer */ > + uint32_t Reserved1; /* Reserved - always set to 0 */ > + uint16_t Reserved2; /* Reserved - always set to 0 */ > + /* Mandatory information for VBE 3.0 and above */ > + uint16_t LinBytesPerScanLine; /* bytes per scan line for linear modes > */ > + uint8_t BnkNumberOfImagePages; /* number of images for banked modes */ > + uint8_t LinNumberOfImagePages; /* number of images for linear modes */ > + /* linear modes */ > + uint8_t LinRedMaskSize; /* size of direct color red mask */ > + uint8_t LinRedFieldPosition; /* bit position of lsb of red mask */ > + uint8_t LinGreenMaskSize; /* size of direct color green mask */ > + uint8_t LinGreenFieldPosition; /* bit position of lsb of green mask */ > + uint8_t LinBlueMaskSize; /* size of direct color blue mask */ > + uint8_t LinBlueFieldPosition; /* bit position of lsb of blue mask */ > + uint8_t LinRsvdMaskSize; /* size of direct color reserved mask */ > + uint8_t LinRsvdFieldPosition; /* bit position of lsb of reserved mask > */ > + uint32_t MaxPixelClock; /* maximum pixel clock > + (in Hz) for graphics mode */ > + uint8_t Reserved3[189]; /* remainder of ModeInfoBlock */ > +} __attribute__((__packed__)) ; > + > +struct VBE_CRTCInfoBlock { > + uint16_t HorizontalTotal; /* Horizontal total in pixels */ > + uint16_t HorizontalSyncStart; /* Horizontal sync start in pixels */ > + uint16_t HorizontalSyncEnd; /* Horizontal sync end in pixels */ > + uint16_t VerticalTotal; /* Vertical total in lines */ > + uint16_t VerticalSyncStart; /* Vertical sync start in lines */ > + uint16_t VerticalSyncEnd; /* Vertical sync end in lines */ > + uint8_t Flags; /* Flags (Interlaced, Double Scan etc) > */ > + uint32_t PixelClock; /* Pixel clock in units of Hz */ > + uint16_t RefreshRate; /* Refresh rate in units of 0.01 Hz */ > + uint8_t Reserved[40]; /* remainder of ModeInfoBlock */ > +} __attribute__((__packed__)) ; > + > +struct VBE_PaletteEntry { > + uint8_t Blue; /* Blue channel value (6 or 8 bits) */ > + uint8_t Green; /* Green channel value (6 or 8 bits) */ > + uint8_t Red; /* Red channel value(6 or 8 bits) */ > + uint8_t Alignment; /* DWORD alignment byte (unused) */ > +} __attribute__((__packed__)) ; > + > +struct VBE_SupVbeInfoBlock { > + uint8_t SupVbeSignature[7]; /* Supplemental VBE Signature */ > + uint16_t SupVbeVersion; /* Supplemental VBE Version */ > + uint8_t SupVbeSubFunc[8]; /* Bitfield of supported subfunctions */ > + uint16_t OemSoftwareRev; /* OEM Software revision */ > + uint8_t *OemVendorNamePtr; /* VbeFarPtr to Vendor Name String */ > + uint8_t *OemProductNamePtr; /* VbeFarPtr to Product Name String */ > + uint8_t *OemProductRevPtr; /* VbeFarPtr to Product Revision String > */ > + uint8_t *OemStringPtr; /* VbeFarPtr to OEM String */ > + uint8_t Reserved[221]; /* Reserved for description > + strings and future */ > + /* expansion */ > +} __attribute__((__packed__)) ; > + > +/* VbeInfoBlock Capabilities */ > +/* D0 = 0 DAC is fixed width, with 6 bits per primary color */ > +/* = 1 DAC width is switchable to 8 bits per primary color */ > +#define VBE_DACswitchableMask 0x0001 > +/* D1 = 0 Controller is VGA compatible */ > +/* = 1 Controller is not VGA compatible */ > +#define VBE_notVGAcompatibleMask 0x0002 > +/* D2 = 0 Normal RAMDAC operation */ > +/* = 1 When programming large blocks of information to the RAMDAC, > + use the blank bit in Function 09h. */ > +#define VBE_specialRAMDACopMask 0x0004 > +/* D3 = 0 No hardware stereoscopic signaling support */ > +/* = 1 Hardware stereoscopic signaling supported by controller */ > +#define VBE_hwStereoscopicMask 0x0008 > +/* D4 = 0 Stereo signaling supported via external VESA stereo connector */ > +/* = 1 Stereo signaling supported via VESA EVC connector */ > +#define VBE_supportEVCconnMask 0x0010 > +/* D5-31 = Reserved */ > + > +/* ModeInfoBlock ModeAttributes */ > +/* D0 = Mode supported by hardware configuration */ > +/* 0 = Mode not supported in hardware */ > +/* 1 = Mode supported in hardware */ > +#define VBE_modSupInHWMask 0x0001 > +/* D1 = 1 (Reserved) */ > +/* D2 = TTY Output functions supported by BIOS */ > +/* 0 = TTY Output functions not supported by BIOS */ > +/* 1 = TTY Output functions supported by BIOS */ > +#define VBE_TTYOutSupByBIOSMask 0x0004 > +/* D3 = Monochrome/color mode (see note below) */ > +/* 0 = Monochrome mode */ > +/* 1 = Color mode */ > +#define VBE_ColorModeMask 0x0008 > +/* D4 = Mode type */ > +/* 0 = Text mode */ > +/* 1 = Graphics mode */ > +#define VBE_GraphicsModeMask 0x0010 > +/* D5 = VGA compatible mode */ > +/* 0 = Yes */ > +/* 1 = No */ > +#define VBE_VGACompModeMask 0x0020 > +/* D6 = VGA compatible windowed memory mode is available */ > +/* 0 = Yes */ > +/* 1 = No */ > +#define VBE_VGACompWinMemModeMask 0x0040 > +/* D7 = Linear frame buffer mode is available */ > +/* 0 = No */ > +/* 1 = Yes */ > +#define VBE_LinFraBufModeAvaiMask 0x0080 > +/* D8 = Double scan mode is available */ > +/* 0 = No */ > +/* 1 = Yes */ > +#define VBE_DblScnModeAvaiMask 0x0100 > +/* D9 = Interlaced mode is available */ > +/* 0 = No */ > +/* 1 = Yes */ > +#define VBE_InterlModeAvaiMask 0x0200 > +/* D10 = Hardware triple buffering support */ > +/* 0 = No */ > +/* 1 = Yes */ > +#define VBE_HWTripBufSupMask 0x0400 > +/* D11 = Hardware stereoscopic display support */ > +/* 0 = No */ > +/* 1 = Yes */ > +#define VBE_HWSterDispSupMask 0x0800 > +/* D12 = Dual display start address support */ > +/* 0 = No */ > +/* 1 = Yes */ > +#define VBE_DualDispStAdrSupMask 0x1000 > +/* D13-D15 = Reserved */ > + > +/* ModeInfoBlock WinXAttributes */ > +/* D0 = Relocatable window(s) supported */ > +/* 0 = Single non-relocatable window only */ > +/* 1 = Relocatable window(s) are supported */ > +#define VBE_RelocWinSupMask 0x01 > +/* D1 = Window readable */ > +/* 0 = Window is not readable */ > +/* 1 = Window is readable */ > +#define VBE_WinReadableMask 0x02 > +/* D2 = Window writeable */ > +/* 0 = Window is not writeable */ > +/* 1 = Window is writeable */ > +#define VBE_WinWritableMask 0x04 > +/* D3-D7 = Reserved */ > + > +/* ModeInfoBlock MemoryModel */ > +#define VBE_TextMode 0x00 > +#define VBE_CGAGraphics 0x01 > +#define VBE_HerculesGraphics 0x02 > +#define VBE_Planar 0x03 > +#define VBE_PackedPixel 0x04 > +#define VBE_NonChain4Color256 0x05 > +#define VBE_DirectColor 0x06 > +#define VBE_YUV 0x07 > + /* 0x08-0x0F Reserved, to be defined by VESA */ > + /* 0x10-0xFF To be defined by OEM */ > + > +/* ModeInfoBlock DirectColorModeInfo */ > +/* D0 = Color ramp is fixed/programmable */ > +/* 0 = Color ramp is fixed */ > +/* 1 = Color ramp is programmable */ > +#define VBE_ColRampProgMask 0x01 > +/* D1 = Bits in Rsvd field are usable/reserved */ > +/* 0 = Bits in Rsvd field are reserved */ > +/* 1 = Bits in Rsvd field are usable by the application */ > +#define VBE_RsvdBitsUsableMask 0x02 > + > +/* CRTCInfoBlock Flags */ > +/* D0 = Double Scan Mode Enable */ > +/* 0 = Graphics mode is not double scanned */ > +/* 1 = Graphics mode is double scanned */ > +#define VBE_GrModeDblScanMask 0x01 > +/* D1 = Interlaced Mode Enable */ > +/* 0 = Graphics mode is non-interlaced */ > +/* 1 = Graphics mode is interlaced */ > +#define VBE_GrModeInterlMask 0x02 > +/* D2 = Horizontal sync polarity */ > +/* 0 = Horizontal sync polarity is positive (+) */ > +/* 1 = Horizontal sync polarity is negative (-) */ > +#define VBE_HorSncPolNegMask 0x04 > +/* D3 = Vertical sync polarity */ > +/* 0 = Vertical sync polarity is positive (+) */ > +/* 1 = Vertical sync polarity is negative (-) */ > +#define VBE_VerSncPolNegMask 0x08 > + > + > +/* VESA BIOS Extensions/Display Data Channel Standard > + Version: 1.1 November 18, 1999 */ > + > +/* VBE/DDC subfunction numbers - passed in BL register */ > +#define VBEDDC_Capabilities 0x0 /* Report VBE/DDC Capabilities */ > +#define VBEDDC_ReadEDID 0x1 /* Read EDID */ > + > +/* DDC Capabilities */ > +/* DDC level supported - returned in BL register */ > +/* 0 - DDC1 not supported; 1 - DDC1 supported */ > +#define VBEDDC_1SupportedMask 0x1 > +/* 0 - DDC2 not supported; 1 - DDC2 supported */ > +#define VBEDDC_2SupportedMask 0x2 > +/* 0 - Screen not blanked during data transfer; > + 1 - Screen blanked during data transfer */ > +#define VBEDDC_scrBlnkDatTrMs 0x4 > + > + > +/* VESA BIOS Extensions/Serial Control Interface Standard > + Version: 1.0 Revision: 2 Date: July 2, 1997 */ > + > +/* VBE/SCI subfunction numbers - passed in BL register */ > +#define VBESCI_ReportCapabil 0x10 /* Report VBE/SCI Capabilities */ > +#define VBESCI_BegSCLSDACtrl 0x11 /* Begin SCL/SDA control */ > +#define VBESCI_EndSCLSDACtrl 0x12 /* End SCL/SDA control */ > +#define VBESCI_WrtSCLClkLine 0x13 /* Write SCL clock line */ > +#define VBESCI_WrtSDADatLine 0x14 /* Write SDA data line */ > +#define VBESCI_RdySCLClkLine 0x15 /* Read SCL clock line */ > +#define VBESCI_RdySDADatLine 0x16 /* Read SDA data line */ > + > +/* SCI Capabilities */ > +/* I2C level supported - returned in BL register */ > +#define VBESCI_capSCLwrtMask 0x1 /* Can write to SCL clock line */ > +#define VBESCI_capSDAwrtMask 0x2 /* Can write to SDA data line */ > +#define VBESCI_capSCLrdyMask 0x4 /* Can read from SCL clock line */ > +#define VBESCI_capSDArdyMask 0x8 /* Can read from SDA data line */ > + > + > +#ifdef __cplusplus > +} > +#endif /* __cplusplus */ > + > +#endif /* ASM */ > + > +#endif /* _VBE_H */ > + > diff --git a/c/src/lib/libbsp/i386/pc386/preinstall.am > b/c/src/lib/libbsp/i386/pc386/preinstall.am > index 1ff9fb8..e02d9d5 100644 > --- a/c/src/lib/libbsp/i386/pc386/preinstall.am > +++ b/c/src/lib/libbsp/i386/pc386/preinstall.am > @@ -147,6 +147,14 @@ $(PROJECT_INCLUDE)/i386_io.h: > ../../i386/shared/comm/i386_io.h $(PROJECT_INCLUDE > $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/i386_io.h > PREINSTALL_FILES += $(PROJECT_INCLUDE)/i386_io.h > > +$(PROJECT_INCLUDE)/vbe3.h: include/vbe3.h $(PROJECT_INCLUDE)/$(dirstamp) > + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/vbe3.h > +PREINSTALL_FILES += $(PROJECT_INCLUDE)/vbe3.h > + > +$(PROJECT_INCLUDE)/edid.h: include/edid.h $(PROJECT_INCLUDE)/$(dirstamp) > + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/edid.h > +PREINSTALL_FILES += $(PROJECT_INCLUDE)/edid.h > + > $(PROJECT_INCLUDE)/pcibios.h: ../../i386/shared/pci/pcibios.h > $(PROJECT_INCLUDE)/$(dirstamp) > $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/pcibios.h > PREINSTALL_FILES += $(PROJECT_INCLUDE)/pcibios.h > -- > 1.9.1 > > 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