Hello Martin, ----- Martin Galvan <martin.gal...@tallertechnologies.com> schrieb: > Hi there! We were looking at the RTEMS SMP support, and wondered what > would it take for the system to support some form of memory protection > (say, an MPU). Is it possible, and if so, how hard would it be?
the question is, what is "some form of memory protection" for you? A process model for RTEMS makes no sense. For this you better use a micro kernel or Linux. The ARMv7-A and some PowerPC BSPs have write protection for code and read-only data. On some BSPs, read/write to the NULL pointer leads to an exception. This is quite handy during development, but offers no real benefit for a production system. For one customer we implemented a stack protection, a thread can only access its own stack, but this is quite non-standard. > > We also saw this: > > https://devel.rtems.org/wiki/Projects/MMU_Support > > What's the status of this project? I don't know. MMU support tends to be highly architecture specific, so the development of a general purpose API is quite difficult. > > On the other hand, we noticed that LEON3 IP Cores usually implement an > MMU instead of just an MPU. Would it be feasible to support that? The GR740 has an IOMMU (chapter 17). http://microelectronics.esa.int/ngmp/GR740-UM-DS-v1.pdf -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.huber at embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel