--- rtemsbsd/include/machine/rtems-bsd-cache.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) mode change 100644 => 100755 rtemsbsd/include/machine/rtems-bsd-cache.h
diff --git a/rtemsbsd/include/machine/rtems-bsd-cache.h b/rtemsbsd/include/machine/rtems-bsd-cache.h old mode 100644 new mode 100755 index b8c4ce7..bd496f9 --- a/rtemsbsd/include/machine/rtems-bsd-cache.h +++ b/rtemsbsd/include/machine/rtems-bsd-cache.h @@ -42,15 +42,12 @@ #include <bsp.h> -#if defined(LIBBSP_ARM_LPC24XX_BSP_H) +#if defined(LIBBSP_ARM_LPC24XX_BSP_H) || (defined(LIBBSP_ARM_LPC32XX_BSP_H) && defined(LPC32XX_DISABLE_MMU)) /* No cache */ #elif defined(LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H) || \ - defined(LIBBSP_ARM_XILINX_ZYNQ_BSP_H) + defined(LIBBSP_ARM_XILINX_ZYNQ_BSP_H) || (defined(LIBBSP_ARM_LPC32XX_BSP_H) && !defined(LPC32XX_DISABLE_MMU)) /* With cache, no coherency support in hardware */ #define CPU_DATA_CACHE_ALIGNMENT 32 -#elif defined(LIBBSP_ARM_LPC32XX_BSP_H) - /* With cache, no coherency support in hardware */ - #include <libcpu/cache.h> #elif defined(__GEN83xx_BSP_h) /* With cache, coherency support in hardware */ #endif -- 1.9.1 _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
