Hello Siegfried,
On 27/03/2020 23:34, Siegfried Giebl wrote:
I am looking for interrupt latency numbers for PowerPC architectures,
if possible for e500v2.
Looking at below postings, there is a mentioning of "TBD" microseconds
as maximum period ... and a variable "na" to describe the value of MHz.
Can you please share your experience ?
I would try to measure the interrupt latency with a test program which
covers your application scenarios. The e500v2 chips are moderately
complex and the timing depends on a lot of parameters (memory chips,
memory controller settings, cache utilization, bus utilization, use of
the 64-bit GPRs, etc.).
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