Hello Fitzsimons, sorry for the late review and thanks Chris for poking me.
I have some troubles understanding the patch and the current code: == Regarding your patch: There is no pin GPMC_AD(18) or GPMC_AD(19). That offset will lead you to the pins GPMC_A8 and GPMC_A9. The correct macros to use would be AM335X_CONF_GPMC_A8 and AM335X_CONF_GPMC_A9. But that's only a style topic. What's a bit odd is that GPMC_A8 seems to be connected to the LED USR3 on the BBB. Reasonable output for a PWM. But GPMC_A9 is a HDMI_INT, which seems a bit odd. == Regarding the old pins The old pins on the other hand (GPMC_AD2 and AD3) are connected to MMC1_DAT2 and 3 which is on P8 pin 5 and 6. That sounds a lot more reasonable. But the pins are definitively not what the pin_no suggests. == What (maybe) should be the correct one P9_14 and P9_16 are EHRPWM1A and EHRPWM1B on the beagle schematic. These are GPMC_AD8 and GPMC_AD9. These pins have a PWM function as an alternative function. So I would expect that you have to use these. It's really hard to find a documentation from TI for the pinmux but I found a list: https://git.ti.com/cgit/sitara-dss-files/am335x-dss-files/tree/padconf/am335x-pinmux.data Can you please double check the registers used in your patch? Best regards Christian On 05/07/2020 12:39, James Fitzsimons wrote: > --- > Fixed incorrect register offset values for EHRPWM1A on P9_14 > and EHRPWM1B on P9_16 > > bsps/arm/beagle/pwm/pwm.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/bsps/arm/beagle/pwm/pwm.c b/bsps/arm/beagle/pwm/pwm.c > index 0bc5d125bf..9a346995aa 100644 > --- a/bsps/arm/beagle/pwm/pwm.c > +++ b/bsps/arm/beagle/pwm/pwm.c > @@ -102,9 +102,9 @@ bool beagle_pwm_pinmux_setup(bbb_pwm_pin_t pin_no, > BBB_PWMSS pwm_id) > } else if (pin_no == BBB_P8_36_1A) { > REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_LCD_DATA(10)) = > BBB_MUXMODE(BBB_P8_36_MUX_PWM); > } else if (pin_no == BBB_P9_14_1A) { > - REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_GPMC_AD(2)) = > BBB_MUXMODE(BBB_P9_14_MUX_PWM); > + REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_GPMC_AD(18)) = > BBB_MUXMODE(BBB_P9_14_MUX_PWM); > } else if (pin_no == BBB_P9_16_1B) { > - REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_GPMC_AD(3)) = > BBB_MUXMODE(BBB_P9_16_MUX_PWM); > + REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_GPMC_AD(19)) = > BBB_MUXMODE(BBB_P9_16_MUX_PWM); > } else { > is_valid = false; > } > _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel