--- This patch was updated after the configuration structs for the STM32 were moved into separate files.
bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h index d423e4f782..715a36d807 100644 --- a/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h +++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h @@ -103,7 +103,9 @@ * (when HSE is used as system clock source, directly or through the PLL). */ #if !defined (HSE_VALUE) -#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */ +//#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */ +// Correction for the STM32H743ZI Nucleo +#define HSE_VALUE ((uint32_t)8000000) #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) -- 2.25.1 >From 4e5c1404ce9277eaadd1b7e697310fc97206000f Mon Sep 17 00:00:00 2001 From: "Robin.Mueller" <robin.muelle...@gmail.com> Date: Wed, 25 Nov 2020 20:16:45 +0100 Subject: [PATCH 02/19] trying to make it externally configurable --- .gitignore | 1 + bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h | 8 ++++++-- spec/build/bsps/arm/stm32h7/opth743nucleo.yml | 13 +++++++++++++ 3 files changed, 20 insertions(+), 2 deletions(-) create mode 100644 spec/build/bsps/arm/stm32h7/opth743nucleo.yml diff --git a/.gitignore b/.gitignore index 8b28b186e1..ec719d4cf0 100644 --- a/.gitignore +++ b/.gitignore @@ -12,3 +12,4 @@ Makefile.in /testsuites/build/build /testsuites/build/wscript .waf* +.project diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h index 715a36d807..ff59180d72 100644 --- a/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h +++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h @@ -103,9 +103,13 @@ * (when HSE is used as system clock source, directly or through the PLL). */ #if !defined (HSE_VALUE) -//#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */ +#ifdef STM32H743ZI_NUCLEO +#define HSE_VALUE ((uint32_t)8000000) +#else +#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */ +#endif // Correction for the STM32H743ZI Nucleo -#define HSE_VALUE ((uint32_t)8000000) + #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) diff --git a/spec/build/bsps/arm/stm32h7/opth743nucleo.yml b/spec/build/bsps/arm/stm32h7/opth743nucleo.yml new file mode 100644 index 0000000000..3e68455893 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/opth743nucleo.yml @@ -0,0 +1,13 @@ +actions: +- get-boolean: null +- define-condition: null +build-type: option +default: false +default-by-variant: [] +enabled-by: true +format: '{}' +links: [] +name: STM32H743ZI_NUCLEO +description: | + Nucleo board. Use 8 MHz HSE external clock. +type: build -- 2.25.1 >From ede140e783479c09fc82a0008651e07b612dc488 Mon Sep 17 00:00:00 2001 From: "Robin.Mueller" <robin.muelle...@gmail.com> Date: Wed, 25 Nov 2020 21:37:31 +0100 Subject: [PATCH 03/19] added build dependency --- spec/build/bsps/arm/stm32h7/bspstm32h7.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/spec/build/bsps/arm/stm32h7/bspstm32h7.yml b/spec/build/bsps/arm/stm32h7/bspstm32h7.yml index 835247316c..d2573d89fe 100644 --- a/spec/build/bsps/arm/stm32h7/bspstm32h7.yml +++ b/spec/build/bsps/arm/stm32h7/bspstm32h7.yml @@ -226,6 +226,8 @@ links: uid: optmemsdram2sz - role: build-dependency uid: optmemsram1sz +- role: build-dependency + uid: opth743nucleo - role: build-dependency uid: optmemsram2sz - role: build-dependency -- 2.25.1 >From bd8359bbd7c3d154f401a1ffdf16d90a6e8b34dd Mon Sep 17 00:00:00 2001 From: "Robin.Mueller" <robin.muelle...@gmail.com> Date: Wed, 25 Nov 2020 21:40:19 +0100 Subject: [PATCH 04/19] moved config option --- spec/build/bsps/arm/stm32h7/bspstm32h7.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/spec/build/bsps/arm/stm32h7/bspstm32h7.yml b/spec/build/bsps/arm/stm32h7/bspstm32h7.yml index d2573d89fe..cd3446d1d4 100644 --- a/spec/build/bsps/arm/stm32h7/bspstm32h7.yml +++ b/spec/build/bsps/arm/stm32h7/bspstm32h7.yml @@ -226,8 +226,6 @@ links: uid: optmemsdram2sz - role: build-dependency uid: optmemsram1sz -- role: build-dependency - uid: opth743nucleo - role: build-dependency uid: optmemsram2sz - role: build-dependency @@ -246,6 +244,8 @@ links: uid: ../../optconsolebaud - role: build-dependency uid: ../../optconsoleirq +- role: build-dependency + uid: opth743nucleo - role: build-dependency uid: ../grp - role: build-dependency -- 2.25.1 >From 706a4542c3bdc963497d6404602dcf24391dea01 Mon Sep 17 00:00:00 2001 From: "Robin.Mueller" <robin.muelle...@gmail.com> Date: Wed, 25 Nov 2020 23:48:36 +0100 Subject: [PATCH 05/19] comment moved --- bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h index ff59180d72..6c840ed12b 100644 --- a/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h +++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h @@ -104,11 +104,11 @@ */ #if !defined (HSE_VALUE) #ifdef STM32H743ZI_NUCLEO +// HSE for the STM32H743ZI Nucleo #define HSE_VALUE ((uint32_t)8000000) #else #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */ #endif -// Correction for the STM32H743ZI Nucleo #endif /* HSE_VALUE */ -- 2.25.1 >From 2d96d82a84ca4f96a1b17406a0aefe07bb52510e Mon Sep 17 00:00:00 2001 From: "Robin.Mueller" <robin.muelle...@gmail.com> Date: Thu, 26 Nov 2020 11:15:38 +0100 Subject: [PATCH 06/19] define not propagated to header --- bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h index 6c840ed12b..a7e0dcaf8b 100644 --- a/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h +++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h @@ -103,11 +103,9 @@ * (when HSE is used as system clock source, directly or through the PLL). */ #if !defined (HSE_VALUE) -#ifdef STM32H743ZI_NUCLEO // HSE for the STM32H743ZI Nucleo #define HSE_VALUE ((uint32_t)8000000) -#else -#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */ +//#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */ #endif #endif /* HSE_VALUE */ -- 2.25.1 >From 51104ac6a5b700a65efb3ecca22b3c5df41a80f5 Mon Sep 17 00:00:00 2001 From: "Robin.Mueller" <robin.muelle...@gmail.com> Date: Thu, 26 Nov 2020 11:25:22 +0100 Subject: [PATCH 07/19] value hardcoded again --- bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h index a7e0dcaf8b..56b45d751f 100644 --- a/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h +++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h @@ -106,8 +106,6 @@ // HSE for the STM32H743ZI Nucleo #define HSE_VALUE ((uint32_t)8000000) //#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */ -#endif - #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) -- 2.25.1 >From b6f27f08107450e832fa2dea30f8e7dae925fd31 Mon Sep 17 00:00:00 2001 From: "Robin.Mueller" <robin.muelle...@gmail.com> Date: Sat, 2 Jan 2021 16:39:25 +0100 Subject: [PATCH 08/19] trying to load bspopts --- bsps/arm/stm32h7/console/console-usart3.c | 19 +++++++++++++++++++ bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h | 8 +++++++- bsps/arm/stm32h7/include/stm32h7xx_hal_uart.h | 1 + 3 files changed, 27 insertions(+), 1 deletion(-) diff --git a/bsps/arm/stm32h7/console/console-usart3.c b/bsps/arm/stm32h7/console/console-usart3.c index 6e0a10fe46..08962dae81 100644 --- a/bsps/arm/stm32h7/console/console-usart3.c +++ b/bsps/arm/stm32h7/console/console-usart3.c @@ -25,12 +25,30 @@ * POSSIBILITY OF SUCH DAMAGE. */ +#include <bspopts.h> + #ifdef HAVE_CONFIG_H #include "config.h" #endif #include <stm32h7/hal.h> +#if STM32H743ZI_NUCLEO == 1 +static const stm32h7_uart_config stm32h7_usart3_config = { + .gpio = { + .regs = GPIOB, + .config = { + .Pin = GPIO_PIN_8 | GPIO_PIN_9, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_FREQ_LOW, + .Alternate = GPIO_AF7_USART3 + } + }, + .irq = USART3_IRQn, + .device_index = 2 +}; +#else static const stm32h7_uart_config stm32h7_usart3_config = { .gpio = { .regs = GPIOB, @@ -45,6 +63,7 @@ static const stm32h7_uart_config stm32h7_usart3_config = { .irq = USART3_IRQn, .device_index = 2 }; +#endif stm32h7_uart_context stm32h7_usart3_instance = { .uart = { diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h index 56b45d751f..4d54f074ba 100644 --- a/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h +++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h @@ -21,6 +21,9 @@ #ifndef __STM32H7xx_HAL_CONF_H #define __STM32H7xx_HAL_CONF_H +//#ifdef __rtems__ +#include <bspopts.h> +//#endif /* __rtems__ */ #ifdef __cplusplus extern "C" { #endif @@ -103,9 +106,12 @@ * (when HSE is used as system clock source, directly or through the PLL). */ #if !defined (HSE_VALUE) +#if STM32H743ZI_NUCLEO == 1 // HSE for the STM32H743ZI Nucleo #define HSE_VALUE ((uint32_t)8000000) -//#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */ +#else +#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */ +#endif #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_uart.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_uart.h index e9fecc4aa0..b171f7dac7 100644 --- a/bsps/arm/stm32h7/include/stm32h7xx_hal_uart.h +++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_uart.h @@ -27,6 +27,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32h7xx_hal_def.h" +#include "stm32h7xx_hal_dma.h" /** @addtogroup STM32H7xx_HAL_Driver * @{ -- 2.25.1 >From 3f460f0073d67f75bdd8ded2c02c0391bef9a131 Mon Sep 17 00:00:00 2001 From: "Robin.Mueller" <robin.muelle...@gmail.com> Date: Sat, 2 Jan 2021 18:51:47 +0100 Subject: [PATCH 09/19] correct uart chosen --- bsps/arm/stm32h7/console/console-usart3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bsps/arm/stm32h7/console/console-usart3.c b/bsps/arm/stm32h7/console/console-usart3.c index 08962dae81..c1b787e71c 100644 --- a/bsps/arm/stm32h7/console/console-usart3.c +++ b/bsps/arm/stm32h7/console/console-usart3.c @@ -36,7 +36,7 @@ #if STM32H743ZI_NUCLEO == 1 static const stm32h7_uart_config stm32h7_usart3_config = { .gpio = { - .regs = GPIOB, + .regs = GPIOD, .config = { .Pin = GPIO_PIN_8 | GPIO_PIN_9, .Mode = GPIO_MODE_AF_PP, -- 2.25.1 >From ce36d0583959c146e48b3215b3b9000bd4a9ab66 Mon Sep 17 00:00:00 2001 From: "Robin.Mueller" <robin.muelle...@gmail.com> Date: Mon, 4 Jan 2021 11:24:03 +0100 Subject: [PATCH 10/19] stm32h7 config --- bsps/arm/stm32h7/start/stm32h7-config.c | 57 +++++++++++++++++++++++ bsps/arm/stm32h7/start/system_stm32h7xx.c | 6 +++ 2 files changed, 63 insertions(+) diff --git a/bsps/arm/stm32h7/start/stm32h7-config.c b/bsps/arm/stm32h7/start/stm32h7-config.c index 874ad047db..ce49f71d8a 100644 --- a/bsps/arm/stm32h7/start/stm32h7-config.c +++ b/bsps/arm/stm32h7/start/stm32h7-config.c @@ -29,11 +29,34 @@ #include "config.h" #endif +//#ifdef __rtems__ +#include <bspopts> +//#endif + #include <stm32h7/hal.h> + const uint32_t stm32h7_config_pwr_regulator_voltagescaling = PWR_REGULATOR_VOLTAGE_SCALE0; +#if STM32H743ZI_NUCLEO == 1 +const RCC_OscInitTypeDef stm32h7_config_oscillator = { + .OscillatorType = RCC_OSCILLATORTYPE_HSE, + .HSEState = RCC_HSE_BYPASS, + .HSIState = RCC_HSI_OFF, + .CSIState = RCC_CSI_OFF, + .PLL.PLLState = RCC_PLL_ON, + .PLL.PLLSource = RCC_PLLSOURCE_HSE, + .PLL.PLLM = 4, + .PLL.PLLN = 400, + .PLL.PLLP = 2, + .PLL.PLLQ = 4, + .PLL.PLLR = 2, + .PLL.PLLRGE = RCC_PLL1VCIRANGE_1, + .PLL.PLLVCOSEL = RCC_PLL1VCOWIDE, + .PLL.PLLFRACN = 0 +}; +#else const RCC_OscInitTypeDef stm32h7_config_oscillator = { .OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_HSI48, @@ -53,6 +76,7 @@ const RCC_OscInitTypeDef stm32h7_config_oscillator = { .PLL.PLLVCOSEL = RCC_PLL1VCOWIDE, .PLL.PLLFRACN = 0 }; +#endif /* STM32H743ZI_NUCLEO == 1 */ const RCC_ClkInitTypeDef stm32h7_config_clocks = { .ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK @@ -69,6 +93,8 @@ const RCC_ClkInitTypeDef stm32h7_config_clocks = { const uint32_t stm32h7_config_flash_latency = FLASH_LATENCY_4; + +#if STM32H743ZI_NUCLEO == 1 const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks = { .PeriphClockSelection = RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 @@ -98,3 +124,34 @@ const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks = { .RTCClockSelection = RCC_RTCCLKSOURCE_LSE, .RngClockSelection = RCC_RNGCLKSOURCE_HSI48 }; +#else +const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks = { + .PeriphClockSelection = RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 + | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 + | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_RNG, + .PLL2.PLL2M = 3, + .PLL2.PLL2N = 48, + .PLL2.PLL2P = 1, + .PLL2.PLL2Q = 2, + .PLL2.PLL2R = 2, + .PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3, + .PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE, + .PLL2.PLL2FRACN = 0, + .PLL3.PLL3M = 25, + .PLL3.PLL3N = 192, + .PLL3.PLL3P = 2, + .PLL3.PLL3Q = 4, + .PLL3.PLL3R = 2, + .PLL3.PLL3RGE = RCC_PLL3VCIRANGE_0, + .PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE, + .PLL3.PLL3FRACN = 0, + .FmcClockSelection = RCC_FMCCLKSOURCE_PLL2, + .FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL, + .Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1, + .Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2, + .I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1, + .UsbClockSelection = RCC_USBCLKSOURCE_PLL3, + .RTCClockSelection = RCC_RTCCLKSOURCE_LSE, + .RngClockSelection = RCC_RNGCLKSOURCE_HSI48 +}; +#endif diff --git a/bsps/arm/stm32h7/start/system_stm32h7xx.c b/bsps/arm/stm32h7/start/system_stm32h7xx.c index 092d853720..65c5a65ef0 100644 --- a/bsps/arm/stm32h7/start/system_stm32h7xx.c +++ b/bsps/arm/stm32h7/start/system_stm32h7xx.c @@ -48,10 +48,16 @@ #include "stm32h7xx.h" #include <math.h> #ifdef __rtems__ +#include <bspopts.h> #include <bsp/linker-symbols.h> #endif /* __rtems__ */ + #if !defined (HSE_VALUE) +#if STM32H743ZI_NUCLEO +#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ +#else #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ +#endif #endif /* HSE_VALUE */ #if !defined (CSI_VALUE) -- 2.25.1 >From d920a820d4ad442dfb10ff733cef43b65b4bdea7 Mon Sep 17 00:00:00 2001 From: "Robin.Mueller" <robin.muelle...@gmail.com> Date: Mon, 4 Jan 2021 12:59:25 +0100 Subject: [PATCH 11/19] reverted stuff and made definitions weak --- bsps/arm/stm32h7/start/stm32h7-config.c | 64 +++---------------------- 1 file changed, 6 insertions(+), 58 deletions(-) diff --git a/bsps/arm/stm32h7/start/stm32h7-config.c b/bsps/arm/stm32h7/start/stm32h7-config.c index ce49f71d8a..22422f2c38 100644 --- a/bsps/arm/stm32h7/start/stm32h7-config.c +++ b/bsps/arm/stm32h7/start/stm32h7-config.c @@ -29,9 +29,9 @@ #include "config.h" #endif -//#ifdef __rtems__ -#include <bspopts> -//#endif +#ifdef __rtems__ +#include <bspopts.h> +#endif #include <stm32h7/hal.h> @@ -39,25 +39,7 @@ const uint32_t stm32h7_config_pwr_regulator_voltagescaling = PWR_REGULATOR_VOLTAGE_SCALE0; -#if STM32H743ZI_NUCLEO == 1 -const RCC_OscInitTypeDef stm32h7_config_oscillator = { - .OscillatorType = RCC_OSCILLATORTYPE_HSE, - .HSEState = RCC_HSE_BYPASS, - .HSIState = RCC_HSI_OFF, - .CSIState = RCC_CSI_OFF, - .PLL.PLLState = RCC_PLL_ON, - .PLL.PLLSource = RCC_PLLSOURCE_HSE, - .PLL.PLLM = 4, - .PLL.PLLN = 400, - .PLL.PLLP = 2, - .PLL.PLLQ = 4, - .PLL.PLLR = 2, - .PLL.PLLRGE = RCC_PLL1VCIRANGE_1, - .PLL.PLLVCOSEL = RCC_PLL1VCOWIDE, - .PLL.PLLFRACN = 0 -}; -#else -const RCC_OscInitTypeDef stm32h7_config_oscillator = { +__attribute__((weak)) const RCC_OscInitTypeDef stm32h7_config_oscillator = { .OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_HSI48, .HSEState = RCC_HSE_ON, @@ -76,9 +58,8 @@ const RCC_OscInitTypeDef stm32h7_config_oscillator = { .PLL.PLLVCOSEL = RCC_PLL1VCOWIDE, .PLL.PLLFRACN = 0 }; -#endif /* STM32H743ZI_NUCLEO == 1 */ -const RCC_ClkInitTypeDef stm32h7_config_clocks = { +__attribute__((weak)) const RCC_ClkInitTypeDef stm32h7_config_clocks = { .ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1, @@ -93,39 +74,7 @@ const RCC_ClkInitTypeDef stm32h7_config_clocks = { const uint32_t stm32h7_config_flash_latency = FLASH_LATENCY_4; - -#if STM32H743ZI_NUCLEO == 1 -const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks = { - .PeriphClockSelection = RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 - | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 - | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_RNG, - .PLL2.PLL2M = 3, - .PLL2.PLL2N = 48, - .PLL2.PLL2P = 1, - .PLL2.PLL2Q = 2, - .PLL2.PLL2R = 2, - .PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3, - .PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE, - .PLL2.PLL2FRACN = 0, - .PLL3.PLL3M = 25, - .PLL3.PLL3N = 192, - .PLL3.PLL3P = 2, - .PLL3.PLL3Q = 4, - .PLL3.PLL3R = 2, - .PLL3.PLL3RGE = RCC_PLL3VCIRANGE_0, - .PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE, - .PLL3.PLL3FRACN = 0, - .FmcClockSelection = RCC_FMCCLKSOURCE_PLL2, - .FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL, - .Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1, - .Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2, - .I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1, - .UsbClockSelection = RCC_USBCLKSOURCE_PLL3, - .RTCClockSelection = RCC_RTCCLKSOURCE_LSE, - .RngClockSelection = RCC_RNGCLKSOURCE_HSI48 -}; -#else -const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks = { +__attribute__((weak)) const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks = { .PeriphClockSelection = RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_RNG, @@ -154,4 +103,3 @@ const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks = { .RTCClockSelection = RCC_RTCCLKSOURCE_LSE, .RngClockSelection = RCC_RNGCLKSOURCE_HSI48 }; -#endif -- 2.25.1 >From 50a549d4938dc2681ec0cf18aa49bd1c74e1d13d Mon Sep 17 00:00:00 2001 From: "Robin.Mueller" <robin.muelle...@gmail.com> Date: Mon, 4 Jan 2021 13:01:31 +0100 Subject: [PATCH 12/19] small tweak --- bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h index 4d54f074ba..7dd73075ba 100644 --- a/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h +++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h @@ -21,9 +21,9 @@ #ifndef __STM32H7xx_HAL_CONF_H #define __STM32H7xx_HAL_CONF_H -//#ifdef __rtems__ +#ifdef __rtems__ #include <bspopts.h> -//#endif /* __rtems__ */ +#endif /* __rtems__ */ #ifdef __cplusplus extern "C" { #endif -- 2.25.1 >From a6675d388e174ad23ce6d61b3084742c056186be Mon Sep 17 00:00:00 2001 From: "Robin.Mueller" <robin.muelle...@gmail.com> Date: Mon, 4 Jan 2021 15:51:39 +0100 Subject: [PATCH 13/19] prepared patch --- bsps/arm/stm32h7/console/console-usart3.c | 23 ++++++++++++++++++- bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h | 8 +++++++ bsps/arm/stm32h7/include/stm32h7xx_hal_uart.h | 1 + bsps/arm/stm32h7/start/stm32h7-config.c | 11 ++++++--- bsps/arm/stm32h7/start/system_stm32h7xx.c | 6 +++++ spec/build/bsps/arm/stm32h7/bspstm32h7.yml | 2 ++ spec/build/bsps/arm/stm32h7/opth743nucleo.yml | 13 +++++++++++ 7 files changed, 60 insertions(+), 4 deletions(-) create mode 100644 spec/build/bsps/arm/stm32h7/opth743nucleo.yml diff --git a/bsps/arm/stm32h7/console/console-usart3.c b/bsps/arm/stm32h7/console/console-usart3.c index 6e0a10fe46..c84f6eb417 100644 --- a/bsps/arm/stm32h7/console/console-usart3.c +++ b/bsps/arm/stm32h7/console/console-usart3.c @@ -25,13 +25,33 @@ * POSSIBILITY OF SUCH DAMAGE. */ +#ifdef __rtems__ +#include <bspopts.h> +#endif + #ifdef HAVE_CONFIG_H #include "config.h" #endif #include <stm32h7/hal.h> -static const stm32h7_uart_config stm32h7_usart3_config = { +#if STM32H743ZI_NUCLEO == 1 +__attribute__((weak)) static const stm32h7_uart_config stm32h7_usart3_config = { + .gpio = { + .regs = GPIOD, + .config = { + .Pin = GPIO_PIN_8 | GPIO_PIN_9, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_FREQ_LOW, + .Alternate = GPIO_AF7_USART3 + } + }, + .irq = USART3_IRQn, + .device_index = 2 +}; +#else +__attribute__((weak)) static const stm32h7_uart_config stm32h7_usart3_config = { .gpio = { .regs = GPIOB, .config = { @@ -45,6 +65,7 @@ static const stm32h7_uart_config stm32h7_usart3_config = { .irq = USART3_IRQn, .device_index = 2 }; +#endif stm32h7_uart_context stm32h7_usart3_instance = { .uart = { diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h index d423e4f782..7dd73075ba 100644 --- a/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h +++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h @@ -21,6 +21,9 @@ #ifndef __STM32H7xx_HAL_CONF_H #define __STM32H7xx_HAL_CONF_H +#ifdef __rtems__ +#include <bspopts.h> +#endif /* __rtems__ */ #ifdef __cplusplus extern "C" { #endif @@ -103,7 +106,12 @@ * (when HSE is used as system clock source, directly or through the PLL). */ #if !defined (HSE_VALUE) +#if STM32H743ZI_NUCLEO == 1 +// HSE for the STM32H743ZI Nucleo +#define HSE_VALUE ((uint32_t)8000000) +#else #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */ +#endif #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_uart.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_uart.h index e9fecc4aa0..b171f7dac7 100644 --- a/bsps/arm/stm32h7/include/stm32h7xx_hal_uart.h +++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_uart.h @@ -27,6 +27,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32h7xx_hal_def.h" +#include "stm32h7xx_hal_dma.h" /** @addtogroup STM32H7xx_HAL_Driver * @{ diff --git a/bsps/arm/stm32h7/start/stm32h7-config.c b/bsps/arm/stm32h7/start/stm32h7-config.c index 874ad047db..22422f2c38 100644 --- a/bsps/arm/stm32h7/start/stm32h7-config.c +++ b/bsps/arm/stm32h7/start/stm32h7-config.c @@ -29,12 +29,17 @@ #include "config.h" #endif +#ifdef __rtems__ +#include <bspopts.h> +#endif + #include <stm32h7/hal.h> + const uint32_t stm32h7_config_pwr_regulator_voltagescaling = PWR_REGULATOR_VOLTAGE_SCALE0; -const RCC_OscInitTypeDef stm32h7_config_oscillator = { +__attribute__((weak)) const RCC_OscInitTypeDef stm32h7_config_oscillator = { .OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_HSI48, .HSEState = RCC_HSE_ON, @@ -54,7 +59,7 @@ const RCC_OscInitTypeDef stm32h7_config_oscillator = { .PLL.PLLFRACN = 0 }; -const RCC_ClkInitTypeDef stm32h7_config_clocks = { +__attribute__((weak)) const RCC_ClkInitTypeDef stm32h7_config_clocks = { .ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1, @@ -69,7 +74,7 @@ const RCC_ClkInitTypeDef stm32h7_config_clocks = { const uint32_t stm32h7_config_flash_latency = FLASH_LATENCY_4; -const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks = { +__attribute__((weak)) const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks = { .PeriphClockSelection = RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_RNG, diff --git a/bsps/arm/stm32h7/start/system_stm32h7xx.c b/bsps/arm/stm32h7/start/system_stm32h7xx.c index 092d853720..65c5a65ef0 100644 --- a/bsps/arm/stm32h7/start/system_stm32h7xx.c +++ b/bsps/arm/stm32h7/start/system_stm32h7xx.c @@ -48,10 +48,16 @@ #include "stm32h7xx.h" #include <math.h> #ifdef __rtems__ +#include <bspopts.h> #include <bsp/linker-symbols.h> #endif /* __rtems__ */ + #if !defined (HSE_VALUE) +#if STM32H743ZI_NUCLEO +#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ +#else #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ +#endif #endif /* HSE_VALUE */ #if !defined (CSI_VALUE) diff --git a/spec/build/bsps/arm/stm32h7/bspstm32h7.yml b/spec/build/bsps/arm/stm32h7/bspstm32h7.yml index 835247316c..cd3446d1d4 100644 --- a/spec/build/bsps/arm/stm32h7/bspstm32h7.yml +++ b/spec/build/bsps/arm/stm32h7/bspstm32h7.yml @@ -244,6 +244,8 @@ links: uid: ../../optconsolebaud - role: build-dependency uid: ../../optconsoleirq +- role: build-dependency + uid: opth743nucleo - role: build-dependency uid: ../grp - role: build-dependency diff --git a/spec/build/bsps/arm/stm32h7/opth743nucleo.yml b/spec/build/bsps/arm/stm32h7/opth743nucleo.yml new file mode 100644 index 0000000000..3e68455893 --- /dev/null +++ b/spec/build/bsps/arm/stm32h7/opth743nucleo.yml @@ -0,0 +1,13 @@ +actions: +- get-boolean: null +- define-condition: null +build-type: option +default: false +default-by-variant: [] +enabled-by: true +format: '{}' +links: [] +name: STM32H743ZI_NUCLEO +description: | + Nucleo board. Use 8 MHz HSE external clock. +type: build -- 2.25.1 >From 4e2645f7586508b0f68e2fb19f888e92d4ac5530 Mon Sep 17 00:00:00 2001 From: "Robin.Mueller" <robin.muelle...@gmail.com> Date: Mon, 4 Jan 2021 16:00:46 +0100 Subject: [PATCH 14/19] functions made public --- bsps/arm/stm32h7/console/console-usart3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bsps/arm/stm32h7/console/console-usart3.c b/bsps/arm/stm32h7/console/console-usart3.c index c84f6eb417..555669436e 100644 --- a/bsps/arm/stm32h7/console/console-usart3.c +++ b/bsps/arm/stm32h7/console/console-usart3.c @@ -36,7 +36,7 @@ #include <stm32h7/hal.h> #if STM32H743ZI_NUCLEO == 1 -__attribute__((weak)) static const stm32h7_uart_config stm32h7_usart3_config = { +__attribute__((weak)) const stm32h7_uart_config stm32h7_usart3_config = { .gpio = { .regs = GPIOD, .config = { @@ -51,7 +51,7 @@ __attribute__((weak)) static const stm32h7_uart_config stm32h7_usart3_config = { .device_index = 2 }; #else -__attribute__((weak)) static const stm32h7_uart_config stm32h7_usart3_config = { +__attribute__((weak)) const stm32h7_uart_config stm32h7_usart3_config = { .gpio = { .regs = GPIOB, .config = { -- 2.25.1 >From 0cb2f4f4deb0015f96866bc00869095b2e637437 Mon Sep 17 00:00:00 2001 From: "Robin.Mueller" <robin.muelle...@gmail.com> Date: Mon, 4 Jan 2021 16:04:03 +0100 Subject: [PATCH 15/19] better help output --- spec/build/bsps/arm/stm32h7/opth743nucleo.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/spec/build/bsps/arm/stm32h7/opth743nucleo.yml b/spec/build/bsps/arm/stm32h7/opth743nucleo.yml index 3e68455893..2c4176bf00 100644 --- a/spec/build/bsps/arm/stm32h7/opth743nucleo.yml +++ b/spec/build/bsps/arm/stm32h7/opth743nucleo.yml @@ -9,5 +9,5 @@ format: '{}' links: [] name: STM32H743ZI_NUCLEO description: | - Nucleo board. Use 8 MHz HSE external clock. + Nucleo board. Use 8 MHz HSE external clock and different pins for the UART console. type: build -- 2.25.1 >From 6ac23279ddc8d8cf5b57c38f7c0e994f225f74af Mon Sep 17 00:00:00 2001 From: "Robin.Mueller" <robin.muelle...@gmail.com> Date: Tue, 5 Jan 2021 12:09:31 +0100 Subject: [PATCH 16/19] merged changes from upstream --- bsps/arm/stm32h7/console/console-uart4-cfg.c | 47 +++++++++++++ bsps/arm/stm32h7/console/console-uart4.c | 15 ---- bsps/arm/stm32h7/console/console-uart5-cfg.c | 47 +++++++++++++ bsps/arm/stm32h7/console/console-uart5.c | 15 ---- bsps/arm/stm32h7/console/console-uart7-cfg.c | 47 +++++++++++++ bsps/arm/stm32h7/console/console-uart7.c | 15 ---- bsps/arm/stm32h7/console/console-uart8-cfg.c | 47 +++++++++++++ bsps/arm/stm32h7/console/console-uart8.c | 15 ---- bsps/arm/stm32h7/console/console-uart9-cfg.c | 51 ++++++++++++++ bsps/arm/stm32h7/console/console-uart9.c | 15 ---- bsps/arm/stm32h7/console/console-usart1-cfg.c | 47 +++++++++++++ bsps/arm/stm32h7/console/console-usart1.c | 15 ---- .../arm/stm32h7/console/console-usart10-cfg.c | 51 ++++++++++++++ bsps/arm/stm32h7/console/console-usart10.c | 15 ---- bsps/arm/stm32h7/console/console-usart2-cfg.c | 47 +++++++++++++ bsps/arm/stm32h7/console/console-usart2.c | 15 ---- bsps/arm/stm32h7/console/console-usart3-cfg.c | 68 +++++++++++++++++++ bsps/arm/stm32h7/console/console-usart3.c | 36 ---------- bsps/arm/stm32h7/console/console-usart6-cfg.c | 47 +++++++++++++ bsps/arm/stm32h7/console/console-usart6.c | 15 ---- bsps/arm/stm32h7/include/stm32h7/hal.h | 20 ++++++ bsps/arm/stm32h7/start/stm32h7-config-clk.c | 45 ++++++++++++ bsps/arm/stm32h7/start/stm32h7-config-fls.c | 34 ++++++++++ bsps/arm/stm32h7/start/stm32h7-config-osc.c | 52 ++++++++++++++ bsps/arm/stm32h7/start/stm32h7-config-per.c | 62 +++++++++++++++++ bsps/arm/stm32h7/start/stm32h7-config-pwr.c | 35 ++++++++++ spec/build/bsps/arm/stm32h7/bspstm32h7.yml | 16 ++++- 27 files changed, 762 insertions(+), 172 deletions(-) create mode 100644 bsps/arm/stm32h7/console/console-uart4-cfg.c create mode 100644 bsps/arm/stm32h7/console/console-uart5-cfg.c create mode 100644 bsps/arm/stm32h7/console/console-uart7-cfg.c create mode 100644 bsps/arm/stm32h7/console/console-uart8-cfg.c create mode 100644 bsps/arm/stm32h7/console/console-uart9-cfg.c create mode 100644 bsps/arm/stm32h7/console/console-usart1-cfg.c create mode 100644 bsps/arm/stm32h7/console/console-usart10-cfg.c create mode 100644 bsps/arm/stm32h7/console/console-usart2-cfg.c create mode 100644 bsps/arm/stm32h7/console/console-usart3-cfg.c create mode 100644 bsps/arm/stm32h7/console/console-usart6-cfg.c create mode 100644 bsps/arm/stm32h7/start/stm32h7-config-clk.c create mode 100644 bsps/arm/stm32h7/start/stm32h7-config-fls.c create mode 100644 bsps/arm/stm32h7/start/stm32h7-config-osc.c create mode 100644 bsps/arm/stm32h7/start/stm32h7-config-per.c create mode 100644 bsps/arm/stm32h7/start/stm32h7-config-pwr.c diff --git a/bsps/arm/stm32h7/console/console-uart4-cfg.c b/bsps/arm/stm32h7/console/console-uart4-cfg.c new file mode 100644 index 0000000000..bef3bf0a4d --- /dev/null +++ b/bsps/arm/stm32h7/console/console-uart4-cfg.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stm32h7/hal.h> + +const stm32h7_uart_config stm32h7_uart4_config = { + .gpio = { + .regs = GPIOH, + .config = { + .Pin = GPIO_PIN_13 | GPIO_PIN_14, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_FREQ_LOW, + .Alternate = GPIO_AF6_UART4 + } + }, + .irq = UART4_IRQn, + .device_index = 3 +}; diff --git a/bsps/arm/stm32h7/console/console-uart4.c b/bsps/arm/stm32h7/console/console-uart4.c index 40536d61cf..ab751d86ce 100644 --- a/bsps/arm/stm32h7/console/console-uart4.c +++ b/bsps/arm/stm32h7/console/console-uart4.c @@ -31,21 +31,6 @@ #include <stm32h7/hal.h> -static const stm32h7_uart_config stm32h7_uart4_config = { - .gpio = { - .regs = GPIOH, - .config = { - .Pin = GPIO_PIN_13 | GPIO_PIN_14, - .Mode = GPIO_MODE_AF_PP, - .Pull = GPIO_NOPULL, - .Speed = GPIO_SPEED_FREQ_LOW, - .Alternate = GPIO_AF6_UART4 - } - }, - .irq = UART4_IRQn, - .device_index = 3 -}; - stm32h7_uart_context stm32h7_uart4_instance = { .uart = { .Instance = UART4, diff --git a/bsps/arm/stm32h7/console/console-uart5-cfg.c b/bsps/arm/stm32h7/console/console-uart5-cfg.c new file mode 100644 index 0000000000..2723f918e7 --- /dev/null +++ b/bsps/arm/stm32h7/console/console-uart5-cfg.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stm32h7/hal.h> + +const stm32h7_uart_config stm32h7_uart5_config = { + .gpio = { + .regs = GPIOD, + .config = { + .Pin = GPIO_PIN_1 | GPIO_PIN_2, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_FREQ_LOW, + .Alternate = GPIO_AF8_UART5 + } + }, + .irq = UART5_IRQn, + .device_index = 4 +}; diff --git a/bsps/arm/stm32h7/console/console-uart5.c b/bsps/arm/stm32h7/console/console-uart5.c index 45b1c04b7c..5c6417f22a 100644 --- a/bsps/arm/stm32h7/console/console-uart5.c +++ b/bsps/arm/stm32h7/console/console-uart5.c @@ -31,21 +31,6 @@ #include <stm32h7/hal.h> -static const stm32h7_uart_config stm32h7_uart5_config = { - .gpio = { - .regs = GPIOD, - .config = { - .Pin = GPIO_PIN_1 | GPIO_PIN_2, - .Mode = GPIO_MODE_AF_PP, - .Pull = GPIO_NOPULL, - .Speed = GPIO_SPEED_FREQ_LOW, - .Alternate = GPIO_AF8_UART5 - } - }, - .irq = UART5_IRQn, - .device_index = 4 -}; - stm32h7_uart_context stm32h7_uart5_instance = { .uart = { .Instance = UART5, diff --git a/bsps/arm/stm32h7/console/console-uart7-cfg.c b/bsps/arm/stm32h7/console/console-uart7-cfg.c new file mode 100644 index 0000000000..640fb358e3 --- /dev/null +++ b/bsps/arm/stm32h7/console/console-uart7-cfg.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stm32h7/hal.h> + +const stm32h7_uart_config stm32h7_uart7_config = { + .gpio = { + .regs = GPIOB, + .config = { + .Pin = GPIO_PIN_3 | GPIO_PIN_4, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_FREQ_LOW, + .Alternate = GPIO_AF7_UART7 + } + }, + .irq = UART7_IRQn, + .device_index = 6 +}; diff --git a/bsps/arm/stm32h7/console/console-uart7.c b/bsps/arm/stm32h7/console/console-uart7.c index eadf7723c6..cc113340c3 100644 --- a/bsps/arm/stm32h7/console/console-uart7.c +++ b/bsps/arm/stm32h7/console/console-uart7.c @@ -31,21 +31,6 @@ #include <stm32h7/hal.h> -static const stm32h7_uart_config stm32h7_uart7_config = { - .gpio = { - .regs = GPIOB, - .config = { - .Pin = GPIO_PIN_3 | GPIO_PIN_4, - .Mode = GPIO_MODE_AF_PP, - .Pull = GPIO_NOPULL, - .Speed = GPIO_SPEED_FREQ_LOW, - .Alternate = GPIO_AF7_UART7 - } - }, - .irq = UART7_IRQn, - .device_index = 6 -}; - stm32h7_uart_context stm32h7_uart7_instance = { .uart = { .Instance = UART7, diff --git a/bsps/arm/stm32h7/console/console-uart8-cfg.c b/bsps/arm/stm32h7/console/console-uart8-cfg.c new file mode 100644 index 0000000000..080de49df4 --- /dev/null +++ b/bsps/arm/stm32h7/console/console-uart8-cfg.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stm32h7/hal.h> + +const stm32h7_uart_config stm32h7_uart8_config = { + .gpio = { + .regs = GPIOE, + .config = { + .Pin = GPIO_PIN_0 | GPIO_PIN_1, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_FREQ_LOW, + .Alternate = GPIO_AF8_UART8 + } + }, + .irq = UART8_IRQn, + .device_index = 7 +}; diff --git a/bsps/arm/stm32h7/console/console-uart8.c b/bsps/arm/stm32h7/console/console-uart8.c index 5daa0e3635..e79d1e4d78 100644 --- a/bsps/arm/stm32h7/console/console-uart8.c +++ b/bsps/arm/stm32h7/console/console-uart8.c @@ -31,21 +31,6 @@ #include <stm32h7/hal.h> -static const stm32h7_uart_config stm32h7_uart8_config = { - .gpio = { - .regs = GPIOE, - .config = { - .Pin = GPIO_PIN_0 | GPIO_PIN_1, - .Mode = GPIO_MODE_AF_PP, - .Pull = GPIO_NOPULL, - .Speed = GPIO_SPEED_FREQ_LOW, - .Alternate = GPIO_AF8_UART8 - } - }, - .irq = UART8_IRQn, - .device_index = 7 -}; - stm32h7_uart_context stm32h7_uart8_instance = { .uart = { .Instance = UART8, diff --git a/bsps/arm/stm32h7/console/console-uart9-cfg.c b/bsps/arm/stm32h7/console/console-uart9-cfg.c new file mode 100644 index 0000000000..a382b869f1 --- /dev/null +++ b/bsps/arm/stm32h7/console/console-uart9-cfg.c @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stm32h7/hal.h> + +#ifdef UART9 + +const stm32h7_uart_config stm32h7_uart9_config = { + .gpio = { + .regs = GPIOB, + .config = { + .Pin = GPIO_PIN_15 | GPIO_PIN_14, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_FREQ_LOW, + .Alternate = GPIO_AF11_UART9 + } + }, + .irq = UART9_IRQn, + .device_index = 8 +}; + +#endif /* UART9 */ diff --git a/bsps/arm/stm32h7/console/console-uart9.c b/bsps/arm/stm32h7/console/console-uart9.c index 821bc11bcc..b6bdcf61f2 100644 --- a/bsps/arm/stm32h7/console/console-uart9.c +++ b/bsps/arm/stm32h7/console/console-uart9.c @@ -33,21 +33,6 @@ #ifdef UART9 -static const stm32h7_uart_config stm32h7_uart9_config = { - .gpio = { - .regs = GPIOB, - .config = { - .Pin = GPIO_PIN_15 | GPIO_PIN_14, - .Mode = GPIO_MODE_AF_PP, - .Pull = GPIO_NOPULL, - .Speed = GPIO_SPEED_FREQ_LOW, - .Alternate = GPIO_AF11_UART9 - } - }, - .irq = UART9_IRQn, - .device_index = 8 -}; - stm32h7_uart_context stm32h7_uart9_instance = { .uart = { .Instance = UART9, diff --git a/bsps/arm/stm32h7/console/console-usart1-cfg.c b/bsps/arm/stm32h7/console/console-usart1-cfg.c new file mode 100644 index 0000000000..47c13b2f54 --- /dev/null +++ b/bsps/arm/stm32h7/console/console-usart1-cfg.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stm32h7/hal.h> + +const stm32h7_uart_config stm32h7_usart1_config = { + .gpio = { + .regs = GPIOB, + .config = { + .Pin = GPIO_PIN_14 | GPIO_PIN_15, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_FREQ_LOW, + .Alternate = GPIO_AF4_USART1 + } + }, + .irq = USART1_IRQn, + .device_index = 0 +}; diff --git a/bsps/arm/stm32h7/console/console-usart1.c b/bsps/arm/stm32h7/console/console-usart1.c index 6dec753d7d..fa83001c33 100644 --- a/bsps/arm/stm32h7/console/console-usart1.c +++ b/bsps/arm/stm32h7/console/console-usart1.c @@ -31,21 +31,6 @@ #include <stm32h7/hal.h> -static const stm32h7_uart_config stm32h7_usart1_config = { - .gpio = { - .regs = GPIOB, - .config = { - .Pin = GPIO_PIN_14 | GPIO_PIN_15, - .Mode = GPIO_MODE_AF_PP, - .Pull = GPIO_NOPULL, - .Speed = GPIO_SPEED_FREQ_LOW, - .Alternate = GPIO_AF4_USART1 - } - }, - .irq = USART1_IRQn, - .device_index = 0 -}; - stm32h7_uart_context stm32h7_usart1_instance = { .uart = { .Instance = USART1, diff --git a/bsps/arm/stm32h7/console/console-usart10-cfg.c b/bsps/arm/stm32h7/console/console-usart10-cfg.c new file mode 100644 index 0000000000..72fe2541f3 --- /dev/null +++ b/bsps/arm/stm32h7/console/console-usart10-cfg.c @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stm32h7/hal.h> + +#ifdef USART10 + +const stm32h7_uart_config stm32h7_usart10_config = { + .gpio = { + .regs = GPIOB, + .config = { + .Pin = GPIO_PIN_15 | GPIO_PIN_14, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_FREQ_LOW, + .Alternate = GPIO_AF11_USART10 + } + }, + .irq = USART10_IRQn, + .device_index = 9 +}; + +#endif /* USART10 */ diff --git a/bsps/arm/stm32h7/console/console-usart10.c b/bsps/arm/stm32h7/console/console-usart10.c index b73346e2cf..7ba2e45433 100644 --- a/bsps/arm/stm32h7/console/console-usart10.c +++ b/bsps/arm/stm32h7/console/console-usart10.c @@ -33,21 +33,6 @@ #ifdef USART10 -static const stm32h7_uart_config stm32h7_usart10_config = { - .gpio = { - .regs = GPIOB, - .config = { - .Pin = GPIO_PIN_15 | GPIO_PIN_14, - .Mode = GPIO_MODE_AF_PP, - .Pull = GPIO_NOPULL, - .Speed = GPIO_SPEED_FREQ_LOW, - .Alternate = GPIO_AF11_USART10 - } - }, - .irq = USART10_IRQn, - .device_index = 9 -}; - stm32h7_uart_context stm32h7_usart10_instance = { .uart = { .Instance = USART10, diff --git a/bsps/arm/stm32h7/console/console-usart2-cfg.c b/bsps/arm/stm32h7/console/console-usart2-cfg.c new file mode 100644 index 0000000000..b17561982b --- /dev/null +++ b/bsps/arm/stm32h7/console/console-usart2-cfg.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stm32h7/hal.h> + +const stm32h7_uart_config stm32h7_usart2_config = { + .gpio = { + .regs = GPIOA, + .config = { + .Pin = GPIO_PIN_2 | GPIO_PIN_3, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_FREQ_LOW, + .Alternate = GPIO_AF7_USART2 + } + }, + .irq = USART2_IRQn, + .device_index = 1 +}; diff --git a/bsps/arm/stm32h7/console/console-usart2.c b/bsps/arm/stm32h7/console/console-usart2.c index 291dbc044d..b14be49d08 100644 --- a/bsps/arm/stm32h7/console/console-usart2.c +++ b/bsps/arm/stm32h7/console/console-usart2.c @@ -31,21 +31,6 @@ #include <stm32h7/hal.h> -static const stm32h7_uart_config stm32h7_usart2_config = { - .gpio = { - .regs = GPIOA, - .config = { - .Pin = GPIO_PIN_2 | GPIO_PIN_3, - .Mode = GPIO_MODE_AF_PP, - .Pull = GPIO_NOPULL, - .Speed = GPIO_SPEED_FREQ_LOW, - .Alternate = GPIO_AF7_USART2 - } - }, - .irq = USART2_IRQn, - .device_index = 1 -}; - stm32h7_uart_context stm32h7_usart2_instance = { .uart = { .Instance = USART2, diff --git a/bsps/arm/stm32h7/console/console-usart3-cfg.c b/bsps/arm/stm32h7/console/console-usart3-cfg.c new file mode 100644 index 0000000000..dc552610e1 --- /dev/null +++ b/bsps/arm/stm32h7/console/console-usart3-cfg.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef __rtems__ +#include <bspopts.h> +#endif + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stm32h7/hal.h> + +#if STM32H743ZI_NUCLEO == 1 +const stm32h7_uart_config stm32h7_usart3_config = { + .gpio = { + .regs = GPIOD, + .config = { + .Pin = GPIO_PIN_8 | GPIO_PIN_9, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_FREQ_LOW, + .Alternate = GPIO_AF7_USART3 + } + }, + .irq = USART3_IRQn, + .device_index = 2 +}; +#else +const stm32h7_uart_config stm32h7_usart3_config = { + .gpio = { + .regs = GPIOB, + .config = { + .Pin = GPIO_PIN_9 | GPIO_PIN_10, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_FREQ_LOW, + .Alternate = GPIO_AF7_USART3 + } + }, + .irq = USART3_IRQn, + .device_index = 2 +}; +#endif /* STM32H743ZI_NUCLEO == 1 */ diff --git a/bsps/arm/stm32h7/console/console-usart3.c b/bsps/arm/stm32h7/console/console-usart3.c index 555669436e..4fb8c7de55 100644 --- a/bsps/arm/stm32h7/console/console-usart3.c +++ b/bsps/arm/stm32h7/console/console-usart3.c @@ -25,48 +25,12 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#ifdef __rtems__ -#include <bspopts.h> -#endif - #ifdef HAVE_CONFIG_H #include "config.h" #endif #include <stm32h7/hal.h> -#if STM32H743ZI_NUCLEO == 1 -__attribute__((weak)) const stm32h7_uart_config stm32h7_usart3_config = { - .gpio = { - .regs = GPIOD, - .config = { - .Pin = GPIO_PIN_8 | GPIO_PIN_9, - .Mode = GPIO_MODE_AF_PP, - .Pull = GPIO_NOPULL, - .Speed = GPIO_SPEED_FREQ_LOW, - .Alternate = GPIO_AF7_USART3 - } - }, - .irq = USART3_IRQn, - .device_index = 2 -}; -#else -__attribute__((weak)) const stm32h7_uart_config stm32h7_usart3_config = { - .gpio = { - .regs = GPIOB, - .config = { - .Pin = GPIO_PIN_9 | GPIO_PIN_10, - .Mode = GPIO_MODE_AF_PP, - .Pull = GPIO_NOPULL, - .Speed = GPIO_SPEED_FREQ_LOW, - .Alternate = GPIO_AF7_USART3 - } - }, - .irq = USART3_IRQn, - .device_index = 2 -}; -#endif - stm32h7_uart_context stm32h7_usart3_instance = { .uart = { .Instance = USART3, diff --git a/bsps/arm/stm32h7/console/console-usart6-cfg.c b/bsps/arm/stm32h7/console/console-usart6-cfg.c new file mode 100644 index 0000000000..f41a2c737f --- /dev/null +++ b/bsps/arm/stm32h7/console/console-usart6-cfg.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stm32h7/hal.h> + +const stm32h7_uart_config stm32h7_usart6_config = { + .gpio = { + .regs = GPIOC, + .config = { + .Pin = GPIO_PIN_6 | GPIO_PIN_7, + .Mode = GPIO_MODE_AF_PP, + .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_FREQ_LOW, + .Alternate = GPIO_AF7_USART6 + } + }, + .irq = USART6_IRQn, + .device_index = 5 +}; diff --git a/bsps/arm/stm32h7/console/console-usart6.c b/bsps/arm/stm32h7/console/console-usart6.c index d43d8dfbf5..91d9d0302f 100644 --- a/bsps/arm/stm32h7/console/console-usart6.c +++ b/bsps/arm/stm32h7/console/console-usart6.c @@ -31,21 +31,6 @@ #include <stm32h7/hal.h> -static const stm32h7_uart_config stm32h7_usart6_config = { - .gpio = { - .regs = GPIOC, - .config = { - .Pin = GPIO_PIN_6 | GPIO_PIN_7, - .Mode = GPIO_MODE_AF_PP, - .Pull = GPIO_NOPULL, - .Speed = GPIO_SPEED_FREQ_LOW, - .Alternate = GPIO_AF7_USART6 - } - }, - .irq = USART6_IRQn, - .device_index = 5 -}; - stm32h7_uart_context stm32h7_usart6_instance = { .uart = { .Instance = USART6, diff --git a/bsps/arm/stm32h7/include/stm32h7/hal.h b/bsps/arm/stm32h7/include/stm32h7/hal.h index fe37f03c04..de38f1a5e8 100644 --- a/bsps/arm/stm32h7/include/stm32h7/hal.h +++ b/bsps/arm/stm32h7/include/stm32h7/hal.h @@ -112,24 +112,44 @@ int stm32h7_uart_polled_read(rtems_termios_device_context *base); extern stm32h7_uart_context stm32h7_usart1_instance; +extern const stm32h7_uart_config stm32h7_usart1_config; + extern stm32h7_uart_context stm32h7_usart2_instance; +extern const stm32h7_uart_config stm32h7_usart2_config; + extern stm32h7_uart_context stm32h7_usart3_instance; +extern const stm32h7_uart_config stm32h7_usart3_config; + extern stm32h7_uart_context stm32h7_uart4_instance; +extern const stm32h7_uart_config stm32h7_uart4_config; + extern stm32h7_uart_context stm32h7_uart5_instance; +extern const stm32h7_uart_config stm32h7_uart5_config; + extern stm32h7_uart_context stm32h7_usart6_instance; +extern const stm32h7_uart_config stm32h7_usart6_config; + extern stm32h7_uart_context stm32h7_uart7_instance; +extern const stm32h7_uart_config stm32h7_uart7_config; + extern stm32h7_uart_context stm32h7_uart8_instance; +extern const stm32h7_uart_config stm32h7_uart8_config; + extern stm32h7_uart_context stm32h7_uart9_instance; +extern const stm32h7_uart_config stm32h7_uart9_config; + extern stm32h7_uart_context stm32h7_usart10_instance; +extern const stm32h7_uart_config stm32h7_usart10_config; + extern const uint32_t stm32h7_config_pwr_regulator_voltagescaling; extern const RCC_OscInitTypeDef stm32h7_config_oscillator; diff --git a/bsps/arm/stm32h7/start/stm32h7-config-clk.c b/bsps/arm/stm32h7/start/stm32h7-config-clk.c new file mode 100644 index 0000000000..3e7c930201 --- /dev/null +++ b/bsps/arm/stm32h7/start/stm32h7-config-clk.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stm32h7/hal.h> + +const RCC_ClkInitTypeDef stm32h7_config_clocks = { + .ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 + | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1, + .SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK, + .SYSCLKDivider = RCC_SYSCLK_DIV1, + .AHBCLKDivider = RCC_HCLK_DIV2, + .APB3CLKDivider = RCC_APB3_DIV2, + .APB1CLKDivider = RCC_APB1_DIV2, + .APB2CLKDivider = RCC_APB2_DIV2, + .APB4CLKDivider = RCC_APB4_DIV2 +}; diff --git a/bsps/arm/stm32h7/start/stm32h7-config-fls.c b/bsps/arm/stm32h7/start/stm32h7-config-fls.c new file mode 100644 index 0000000000..f2d10d2410 --- /dev/null +++ b/bsps/arm/stm32h7/start/stm32h7-config-fls.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stm32h7/hal.h> + +const uint32_t stm32h7_config_flash_latency = FLASH_LATENCY_4; diff --git a/bsps/arm/stm32h7/start/stm32h7-config-osc.c b/bsps/arm/stm32h7/start/stm32h7-config-osc.c new file mode 100644 index 0000000000..b639c7ca36 --- /dev/null +++ b/bsps/arm/stm32h7/start/stm32h7-config-osc.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stm32h7/hal.h> + +const RCC_OscInitTypeDef stm32h7_config_oscillator = { + .OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE + | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_HSI48, + .HSEState = RCC_HSE_ON, + .LSEState = RCC_LSE_ON, + .HSIState = RCC_HSI_DIV1, + .HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT, + .HSI48State = RCC_HSI48_ON, + .PLL.PLLState = RCC_PLL_ON, + .PLL.PLLSource = RCC_PLLSOURCE_HSE, + .PLL.PLLM = 5, + .PLL.PLLN = 192, + .PLL.PLLP = 2, + .PLL.PLLQ = 12, + .PLL.PLLR = 2, + .PLL.PLLRGE = RCC_PLL1VCIRANGE_2, + .PLL.PLLVCOSEL = RCC_PLL1VCOWIDE, + .PLL.PLLFRACN = 0 +}; diff --git a/bsps/arm/stm32h7/start/stm32h7-config-per.c b/bsps/arm/stm32h7/start/stm32h7-config-per.c new file mode 100644 index 0000000000..79aa1494dd --- /dev/null +++ b/bsps/arm/stm32h7/start/stm32h7-config-per.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stm32h7/hal.h> + +const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks = { + .PeriphClockSelection = RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 + | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 + | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_RNG, + .PLL2.PLL2M = 3, + .PLL2.PLL2N = 48, + .PLL2.PLL2P = 1, + .PLL2.PLL2Q = 2, + .PLL2.PLL2R = 2, + .PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3, + .PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE, + .PLL2.PLL2FRACN = 0, + .PLL3.PLL3M = 25, + .PLL3.PLL3N = 192, + .PLL3.PLL3P = 2, + .PLL3.PLL3Q = 4, + .PLL3.PLL3R = 2, + .PLL3.PLL3RGE = RCC_PLL3VCIRANGE_0, + .PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE, + .PLL3.PLL3FRACN = 0, + .FmcClockSelection = RCC_FMCCLKSOURCE_PLL2, + .FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL, + .Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1, + .Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2, + .I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1, + .UsbClockSelection = RCC_USBCLKSOURCE_PLL3, + .RTCClockSelection = RCC_RTCCLKSOURCE_LSE, + .RngClockSelection = RCC_RNGCLKSOURCE_HSI48 +}; diff --git a/bsps/arm/stm32h7/start/stm32h7-config-pwr.c b/bsps/arm/stm32h7/start/stm32h7-config-pwr.c new file mode 100644 index 0000000000..3fcdeba2e8 --- /dev/null +++ b/bsps/arm/stm32h7/start/stm32h7-config-pwr.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <stm32h7/hal.h> + +const uint32_t stm32h7_config_pwr_regulator_voltagescaling = + PWR_REGULATOR_VOLTAGE_SCALE0; diff --git a/spec/build/bsps/arm/stm32h7/bspstm32h7.yml b/spec/build/bsps/arm/stm32h7/bspstm32h7.yml index cd3446d1d4..71a19cdbb9 100644 --- a/spec/build/bsps/arm/stm32h7/bspstm32h7.yml +++ b/spec/build/bsps/arm/stm32h7/bspstm32h7.yml @@ -270,15 +270,25 @@ source: - bsps/arm/shared/start/bsp-start-memcpy.S - bsps/arm/stm32h7/console/console.c - bsps/arm/stm32h7/console/console-uart4.c +- bsps/arm/stm32h7/console/console-uart4-cfg.c - bsps/arm/stm32h7/console/console-uart5.c +- bsps/arm/stm32h7/console/console-uart5-cfg.c - bsps/arm/stm32h7/console/console-uart7.c +- bsps/arm/stm32h7/console/console-uart7-cfg.c - bsps/arm/stm32h7/console/console-uart8.c +- bsps/arm/stm32h7/console/console-uart8-cfg.c - bsps/arm/stm32h7/console/console-uart9.c +- bsps/arm/stm32h7/console/console-uart9-cfg.c - bsps/arm/stm32h7/console/console-usart10.c +- bsps/arm/stm32h7/console/console-usart10-cfg.c - bsps/arm/stm32h7/console/console-usart1.c +- bsps/arm/stm32h7/console/console-usart1-cfg.c - bsps/arm/stm32h7/console/console-usart2.c +- bsps/arm/stm32h7/console/console-usart2-cfg.c - bsps/arm/stm32h7/console/console-usart3.c +- bsps/arm/stm32h7/console/console-usart3-cfg.c - bsps/arm/stm32h7/console/console-usart6.c +- bsps/arm/stm32h7/console/console-usart6-cfg.c - bsps/arm/stm32h7/console/printk-support.c - bsps/arm/stm32h7/hal/stm32h7xx_hal_adc.c - bsps/arm/stm32h7/hal/stm32h7xx_hal_adc_ex.c @@ -400,7 +410,11 @@ source: - bsps/arm/stm32h7/start/ext-mem-ctl.c - bsps/arm/stm32h7/start/getentropy-rng.c - bsps/arm/stm32h7/start/mpu-config.c -- bsps/arm/stm32h7/start/stm32h7-config.c +- bsps/arm/stm32h7/start/stm32h7-config-clk.c +- bsps/arm/stm32h7/start/stm32h7-config-fls.c +- bsps/arm/stm32h7/start/stm32h7-config-osc.c +- bsps/arm/stm32h7/start/stm32h7-config-per.c +- bsps/arm/stm32h7/start/stm32h7-config-pwr.c - bsps/arm/stm32h7/start/stm32h7-hal.c - bsps/arm/stm32h7/start/stm32h7-hal-eth.c - bsps/arm/stm32h7/start/stm32h7-hal-uart.c -- 2.25.1 >From d63a12b6fde4c6025be5e755bb4fde547f968979 Mon Sep 17 00:00:00 2001 From: "Robin.Mueller" <robin.muelle...@gmail.com> Date: Tue, 5 Jan 2021 12:10:37 +0100 Subject: [PATCH 17/19] reverted gitignore change --- .gitignore | 1 - 1 file changed, 1 deletion(-) diff --git a/.gitignore b/.gitignore index ec719d4cf0..8b28b186e1 100644 --- a/.gitignore +++ b/.gitignore @@ -12,4 +12,3 @@ Makefile.in /testsuites/build/build /testsuites/build/wscript .waf* -.project -- 2.25.1 >From 2da3db8799018e98d2237ee54b13f163690fbeb2 Mon Sep 17 00:00:00 2001 From: "Robin.Mueller" <robin.muelle...@gmail.com> Date: Tue, 5 Jan 2021 12:13:03 +0100 Subject: [PATCH 18/19] removed some moved components --- bsps/arm/stm32h7/start/stm32h7-config.c | 67 ------------------------- 1 file changed, 67 deletions(-) diff --git a/bsps/arm/stm32h7/start/stm32h7-config.c b/bsps/arm/stm32h7/start/stm32h7-config.c index 22422f2c38..7dda17cd60 100644 --- a/bsps/arm/stm32h7/start/stm32h7-config.c +++ b/bsps/arm/stm32h7/start/stm32h7-config.c @@ -29,77 +29,10 @@ #include "config.h" #endif -#ifdef __rtems__ -#include <bspopts.h> -#endif - #include <stm32h7/hal.h> - const uint32_t stm32h7_config_pwr_regulator_voltagescaling = PWR_REGULATOR_VOLTAGE_SCALE0; -__attribute__((weak)) const RCC_OscInitTypeDef stm32h7_config_oscillator = { - .OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE - | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_HSI48, - .HSEState = RCC_HSE_ON, - .LSEState = RCC_LSE_ON, - .HSIState = RCC_HSI_DIV1, - .HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT, - .HSI48State = RCC_HSI48_ON, - .PLL.PLLState = RCC_PLL_ON, - .PLL.PLLSource = RCC_PLLSOURCE_HSE, - .PLL.PLLM = 5, - .PLL.PLLN = 192, - .PLL.PLLP = 2, - .PLL.PLLQ = 12, - .PLL.PLLR = 2, - .PLL.PLLRGE = RCC_PLL1VCIRANGE_2, - .PLL.PLLVCOSEL = RCC_PLL1VCOWIDE, - .PLL.PLLFRACN = 0 -}; - -__attribute__((weak)) const RCC_ClkInitTypeDef stm32h7_config_clocks = { - .ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK - | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 - | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1, - .SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK, - .SYSCLKDivider = RCC_SYSCLK_DIV1, - .AHBCLKDivider = RCC_HCLK_DIV2, - .APB3CLKDivider = RCC_APB3_DIV2, - .APB1CLKDivider = RCC_APB1_DIV2, - .APB2CLKDivider = RCC_APB2_DIV2, - .APB4CLKDivider = RCC_APB4_DIV2 -}; - const uint32_t stm32h7_config_flash_latency = FLASH_LATENCY_4; -__attribute__((weak)) const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks = { - .PeriphClockSelection = RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 - | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 - | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_RNG, - .PLL2.PLL2M = 3, - .PLL2.PLL2N = 48, - .PLL2.PLL2P = 1, - .PLL2.PLL2Q = 2, - .PLL2.PLL2R = 2, - .PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3, - .PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE, - .PLL2.PLL2FRACN = 0, - .PLL3.PLL3M = 25, - .PLL3.PLL3N = 192, - .PLL3.PLL3P = 2, - .PLL3.PLL3Q = 4, - .PLL3.PLL3R = 2, - .PLL3.PLL3RGE = RCC_PLL3VCIRANGE_0, - .PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE, - .PLL3.PLL3FRACN = 0, - .FmcClockSelection = RCC_FMCCLKSOURCE_PLL2, - .FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL, - .Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1, - .Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2, - .I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1, - .UsbClockSelection = RCC_USBCLKSOURCE_PLL3, - .RTCClockSelection = RCC_RTCCLKSOURCE_LSE, - .RngClockSelection = RCC_RNGCLKSOURCE_HSI48 -}; -- 2.25.1 >From 8bcd2c40ac28bf575d6e012c57e3546799eefb40 Mon Sep 17 00:00:00 2001 From: "Robin.Mueller" <robin.muelle...@gmail.com> Date: Tue, 5 Jan 2021 12:16:19 +0100 Subject: [PATCH 19/19] deleted old cfg file --- bsps/arm/stm32h7/start/stm32h7-config.c | 38 ------------------------- 1 file changed, 38 deletions(-) delete mode 100644 bsps/arm/stm32h7/start/stm32h7-config.c diff --git a/bsps/arm/stm32h7/start/stm32h7-config.c b/bsps/arm/stm32h7/start/stm32h7-config.c deleted file mode 100644 index 7dda17cd60..0000000000 --- a/bsps/arm/stm32h7/start/stm32h7-config.c +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifdef HAVE_CONFIG_H -#include "config.h" -#endif - -#include <stm32h7/hal.h> - -const uint32_t stm32h7_config_pwr_regulator_voltagescaling = - PWR_REGULATOR_VOLTAGE_SCALE0; - -const uint32_t stm32h7_config_flash_latency = FLASH_LATENCY_4; - -- 2.25.1 _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel