On Mon, Apr 12, 2021 at 1:40 PM Jiri Gaisler <j...@gaisler.se> wrote: > > > On 4/12/21 8:44 PM, Gedare Bloom wrote: > > Hi Jiri, > > > > How much do you think this is a RISC-V specific problem, or one that > > may affect other SMP processors? Should we add an RTEMS API for this > > capability instead of shimming some Asm into a test case? > > It's bound to happen on any architecture/loader that starts all processor > cores before jumping to RTEMS. Leon3 and Griscv only start on core so the > test passes, while 'regular' RISCV will fail as all cores are started by the > loader. I do not now how the other SMP architectures (x86, PowerPC, ARM) work > during start-up. Note that this specific test bypasses most of the normal SMP > start-up, that's why the problem occurs. I really don't think we need a > special API for this. > > I just realized that I can change the patch from an assembly WFI to a simple > busy loop instead. This would work on any architecture without assembly. > Should I provide a new patch with this cleaner solution? > Yes, and a comment in the code please
> Jiri. > > > > > On Sun, Apr 11, 2021 at 1:30 PM Jiri Gaisler <j...@gaisler.se> wrote: > >> smpfatal08 fails on SMP RISC-V systems because all cpus are started by the > >> boot-loader and clobber the test output. This patch stops the secondary > >> cpus with a WFI (wait-for-interrupt). Harmless if only one cpu is started > >> by the loader, as in the griscv bsp. > >> > >> _______________________________________________ > >> devel mailing list > >> devel@rtems.org > >> http://lists.rtems.org/mailman/listinfo/devel > _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
