On 01/10/2021 21:39, Kinsey Moore wrote:
Sebastian,
Could you be more specific about which parts of the
architecture-dependent interface still seem tied to the AArch64 port? I
thought I had made them sufficiently abstract by relying on
architecture-specific functions to manipulate and take action on the
exception frame. The signal mapping code written on top of this should
work for any architecture that implements those functions and contains
no reliance on architecture that I can see. The set of exception classes
in particular includes exceptions that don't exist on AArch64, but were
added because they're known to be present on SPARC and need to be
handled. I'm only really familiar with ARM and AArch64, so that could be
why I'm missing it.
I would provide a new CPU feature flag
#define CPU_HAS_EXCEPTION_TO_SIGNAL_MAPPING TRUE|FALSE
If it is TRUE, then the CPU port shall provide:
/**
* @retval -1 There is no signal associated with the exception.
* @retval SIGSEGV, SIGFPE, ...
*/
int _CPU_Exception_frame_get_signal( const CPU_Exception_frame *frame );
RTEMS_NO_RETURN _CPU_Exception_resume( CPU_Exception_frame *frame );
The architecture-independent part just needs to provide a fatal extension:
_Thread_local Thread_Action _Exception_Raise_signal_action;
void _Exception_Raise_signal( source, true, code )
{
int sig;
if ( source != RTEMS_FATAL_SOURCE_EXCEPTION ) {
return;
}
sig = _CPU_Exception_frame_get_signal( code );
switch ( sig ) {
case SIGSEGV:
handler = _Exception_Raise_sigsegv;
break;
default:
return;
}
_Thread_Prepend_post_switch_action( executing,
&_Exception_Raise_signal_action, handler );
_CPU_Exception_resume( code );
}
Using a post-switch extension has the benefit that you don't have to
call the complicated raise() function in the exception context. It is
called in thread context.
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