On 2/11/2022 5:38 am, Kinsey Moore wrote:> +#ifdef BSP_XILINX_ZYNQMP_MGMT_UART_BASE > +/** > + * @brief Zynq UltraScale+ MPSoC specific set up of a management console. > + * > + * The ZynqMP SoC's programmable logic can provide a serial interface for > system > + * management which may need special initialization. Provide in the > application > + * to override the defaults in the BSP. > + */
I am not comfortable with PL implementation dependences for specific hardware being added to the generic BSP code. The Zynq, ZymqMP and Versal have so far only referenced the hard IP. Is the PL project and implementation for the PL logic openly available? The hardware requires I request a data sheet from the manufacturer and that makes keeping this code in our open repo difficult. Chris _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
