Add support for MDIO drivers. This is just a first step to unify the
PHY/MDIO support in cpsw and uLan. Defining a proper API needs more
work.
---
cpsw/src/include/hw_mdio.h | 21 +++
cpsw/src/include/mdio.h | 59 ++++---
cpsw/src/include/phy.h | 26 +--
cpsw/src/netif/cpswif.c | 47 +++---
cpsw/src/netif/mdio.c | 58 ++-----
cpsw/src/netif/phy.c | 100 +++++------
uLan/ports/driver/tms570_emac/phy_dp83848h.c | 80 ++++-----
uLan/ports/driver/tms570_emac/phy_dp83848h.h | 26 +--
uLan/ports/driver/tms570_emac/ti_drv_mdio.h | 167 -------------------
uLan/ports/driver/tms570_emac/tms570_emac.h | 5 +-
uLan/ports/driver/tms570_emac/tms570_netif.c | 26 +--
11 files changed, 239 insertions(+), 376 deletions(-)
delete mode 100644 uLan/ports/driver/tms570_emac/ti_drv_mdio.h
diff --git a/cpsw/src/include/hw_mdio.h b/cpsw/src/include/hw_mdio.h
index 1372a1d..e05200d 100755
--- a/cpsw/src/include/hw_mdio.h
+++ b/cpsw/src/include/hw_mdio.h
@@ -43,6 +43,10 @@
#ifndef _HW_MDIO_H_
#define _HW_MDIO_H_
+#include "mdio.h"
+
+#include <stdint.h>
+
#ifdef __cplusplus
extern "C" {
#endif
@@ -249,6 +253,23 @@ extern "C" {
#define MDIO_USERPHYSEL1_PHYADRMON (0x0000001Fu)
#define MDIO_USERPHYSEL1_PHYADRMON_SHIFT (0x00000000u)
+typedef struct {
+ mdioControl base;
+ uintptr_t baseAddr;
+} tiMDIOControl;
+
+void TIMDIOInit(mdioControl *self, unsigned int mdioInputFreq,
+ unsigned int mdioOutputFreq);
+
+unsigned int TIMDIOPhyAliveStatusGet(mdioControl *self);
+
+unsigned int TIMDIOPhyLinkStatusGet(mdioControl *self);
+
+unsigned int TIMDIOPhyRegRead(mdioControl *self,
+ unsigned int phyAddr, unsigned int regNum, unsigned short *dataPtr);
+
+void TIMDIOPhyRegWrite(mdioControl *self, unsigned int phyAddr,
+ unsigned int regNum, unsigned short regVal);
#ifdef __cplusplus
}
diff --git a/cpsw/src/include/mdio.h b/cpsw/src/include/mdio.h
index 7b3c64c..326683a 100755
--- a/cpsw/src/include/mdio.h
+++ b/cpsw/src/include/mdio.h
@@ -43,32 +43,53 @@
#ifndef __MDIO_H__
#define __MDIO_H__
-#include "hw_mdio.h"
-
#ifdef __cplusplus
extern "C" {
#endif
-/*****************************************************************************/
-/*
-** Structure to save CPSW context
-*/
-typedef struct mdioContext {
- unsigned int mdioCtrl;
-}MDIOCONTEXT;
+
+typedef struct mdioControl {
+ void (*init)(struct mdioControl *self, unsigned int mdioInputFreq,
+ unsigned int mdioOutputFreq);
+ unsigned int (*phyAliveStatusGet)(struct mdioControl *self);
+ unsigned int (*phyLinkStatusGet)(struct mdioControl *self);
+ unsigned int (*phyRegRead)(struct mdioControl *self, unsigned int phyAddr,
+ unsigned int regNum, unsigned short *dataPtr);
+ void (*phyRegWrite)(struct mdioControl *self, unsigned int phyAddr,
+ unsigned int regNum, unsigned short RegVal);
+} mdioControl;
/*
** Prototypes for the APIs
*/
-extern unsigned int MDIOPhyAliveStatusGet(unsigned int baseAddr);
-extern unsigned int MDIOPhyLinkStatusGet(unsigned int baseAddr);
-extern void MDIOInit(unsigned int baseAddr, unsigned int mdioInputFreq,
- unsigned int mdioOutputFreq);
-extern unsigned int MDIOPhyRegRead(unsigned int baseAddr, unsigned int phyAddr,
- unsigned int regNum, volatile unsigned
short *dataPtr);
-extern void MDIOPhyRegWrite(unsigned int baseAddr, unsigned int phyAddr,
- unsigned int regNum, unsigned short RegVal);
-extern void MDIOContextSave(unsigned int baseAddr, MDIOCONTEXT *contextPtr);
-extern void MDIOContextRestore(unsigned int baseAddr, MDIOCONTEXT *contextPtr);
+
+static inline void MDIOInit(mdioControl *self, unsigned int mdioInputFreq,
+ unsigned int mdioOutputFreq)
+{
+ return (*self->init)(self, mdioInputFreq, mdioOutputFreq);
+}
+
+static inline unsigned int MDIOPhyAliveStatusGet(mdioControl *self)
+{
+ return (*self->phyAliveStatusGet)(self);
+}
+
+static inline unsigned int MDIOPhyLinkStatusGet(mdioControl *self)
+{
+ return (*self->phyLinkStatusGet)(self);
+}
+
+static inline unsigned int MDIOPhyRegRead(mdioControl *self,
+ unsigned int phyAddr, unsigned int regNum, unsigned short *dataPtr)
+{
+ return (*self->phyRegRead)(self, phyAddr, regNum, dataPtr);
+}
+
+static inline void MDIOPhyRegWrite(mdioControl *self, unsigned int phyAddr,
+ unsigned int regNum, unsigned short regVal)
+{
+ return (*self->phyRegWrite)(self, phyAddr, regNum, regVal);
+}
+
#ifdef __cplusplus
}
#endif
diff --git a/cpsw/src/include/phy.h b/cpsw/src/include/phy.h
index 26292bb..3d2caa2 100755
--- a/cpsw/src/include/phy.h
+++ b/cpsw/src/include/phy.h
@@ -42,6 +42,8 @@
#ifndef _PHY_H_
#define _PHY_H_
+#include "mdio.h"
+
#ifdef __cplusplus
extern "C" {
#endif
@@ -113,37 +115,37 @@ extern "C" {
/**************************************************************************
API function Prototypes
**************************************************************************/
-extern unsigned int PhyIDGet(unsigned int mdioBaseAddr,
+extern unsigned int PhyIDGet(mdioControl *mdio,
unsigned int phyAddr);
-extern unsigned int PhyLoopBackEnable(unsigned int mdioBaseAddr,
+extern unsigned int PhyLoopBackEnable(mdioControl *mdio,
unsigned int phyAddr);
-extern unsigned int PhyLoopBackDisable(unsigned int mdioBaseAddr,
+extern unsigned int PhyLoopBackDisable(mdioControl *mdio,
unsigned int phyAddr);
-extern unsigned int PhyReset(unsigned int mdioBaseAddr, unsigned int phyAddr);
-extern unsigned int PhyConfigure(unsigned int mdioBaseAddr,
+extern unsigned int PhyReset(mdioControl *mdio, unsigned int phyAddr);
+extern unsigned int PhyConfigure(mdioControl *mdio,
unsigned int phyAddr,
unsigned short speed,
unsigned short duplexMode);
-extern unsigned int PhyAutoNegotiate(unsigned int mdioBaseAddr,
+extern unsigned int PhyAutoNegotiate(mdioControl *mdio,
unsigned int phyAddr,
unsigned short *advPtr,
unsigned short *gigAdvPtr);
-extern unsigned int PhyRegRead(unsigned int mdioBaseAddr,
+extern unsigned int PhyRegRead(mdioControl *mdio,
unsigned int phyAddr,
unsigned int regIdx,
unsigned short *regValAdr);
-extern void PhyRegWrite(unsigned int mdioBaseAddr,
+extern void PhyRegWrite(mdioControl *mdio,
unsigned int phyAddr,
unsigned int regIdx,
unsigned short regVal);
-extern unsigned int PhyPartnerAbilityGet(unsigned int mdioBaseAddr,
+extern unsigned int PhyPartnerAbilityGet(mdioControl *mdio,
unsigned int phyAddr,
unsigned short *ptnerAblty,
unsigned short *gbpsPtnerAblty);
-extern unsigned int PhyLinkStatusGet(unsigned int mdioBaseAddr,
+extern unsigned int PhyLinkStatusGet(mdioControl *mdio,
unsigned int phyAddr,
- volatile unsigned int retries);
-extern unsigned int PhyAutoNegStatusGet(unsigned int mdioBaseAddr,
+ unsigned int retries);
+extern unsigned int PhyAutoNegStatusGet(mdioControl *mdio,
unsigned int phyAddr);
#ifdef __cplusplus
}
diff --git a/cpsw/src/netif/cpswif.c b/cpsw/src/netif/cpswif.c
index 9ff45b0..e2df35c 100755
--- a/cpsw/src/netif/cpswif.c
+++ b/cpsw/src/netif/cpswif.c
@@ -61,7 +61,7 @@
/* DriverLib Header Files required for this interface driver. */
#include "cpsw.h"
-#include "mdio.h"
+#include "hw_mdio.h"
#include "delay.h"
#include "phy.h"
#include "cache.h"
@@ -269,7 +269,7 @@ struct cpswport{
struct cpswinst{
/* Base addresses */
u32_t ss_base;
- u32_t mdio_base;
+ tiMDIOControl mdio;
u32_t wrpr_base;
u32_t ale_base;
u32_t cpdma_base;
@@ -308,7 +308,12 @@ cpswif_inst_config(struct cpswportif *cpswif) {
*/
if(0 == inst_num) {
cpswinst->ss_base = CPSW0_SS_REGS;
- cpswinst->mdio_base = CPSW0_MDIO_REGS;
+ cpswinst->mdio.base.init = TIMDIOInit;
+ cpswinst->mdio.base.phyAliveStatusGet = TIMDIOPhyAliveStatusGet;
+ cpswinst->mdio.base.phyLinkStatusGet = TIMDIOPhyLinkStatusGet;
+ cpswinst->mdio.base.phyRegRead = TIMDIOPhyRegRead;
+ cpswinst->mdio.base.phyRegWrite = TIMDIOPhyRegWrite;
+ cpswinst->mdio.baseAddr = CPSW0_MDIO_REGS;
cpswinst->wrpr_base = CPSW0_WR_REGS;
cpswinst->cpdma_base = CPSW0_CPDMA_REGS;
cpswinst->ale_base = CPSW0_ALE_REGS;
@@ -1166,7 +1171,7 @@ cpswif_phy_autoneg(struct cpswinst *cpswinst, u32_t
port_num, u32_t adv) {
u32_t aut_neg_cnt = 200, auto_stat, transfer_mode = 0;
/* Check if ethernet PHY is present or not */
- if (0 == (MDIOPhyAliveStatusGet(cpswinst->mdio_base)
+ if (0 == (MDIOPhyAliveStatusGet(&cpswinst->mdio.base)
& (1 << cpswinst->port[port_num - 1].phy_addr))) {
LWIP_PRINTF("\n\rNo PHY found at addr %d for Port %d of Instance %d.",
cpswinst->port[port_num - 1].phy_addr,
@@ -1221,12 +1226,12 @@ cpswif_phy_autoneg(struct cpswinst *cpswinst, u32_t
port_num, u32_t adv) {
* Now start Autonegotiation. PHY will talk to its partner
* and give us what the partner can handle
*/
- if (PhyAutoNegotiate(cpswinst->mdio_base,
+ if (PhyAutoNegotiate(&cpswinst->mdio.base,
cpswinst->port[port_num -1].phy_addr,
&adv_val, &gig_adv_val) == TRUE) {
while (aut_neg_cnt) {
delay(50);
- auto_stat = PhyAutoNegStatusGet(cpswinst->mdio_base,
+ auto_stat = PhyAutoNegStatusGet(&cpswinst->mdio.base,
cpswinst->port[port_num -1].phy_addr);
if (TRUE == auto_stat) {
break;
@@ -1243,7 +1248,7 @@ cpswif_phy_autoneg(struct cpswinst *cpswinst, u32_t
port_num, u32_t adv) {
}
/* Get what the partner supports */
- PhyPartnerAbilityGet(cpswinst->mdio_base,
+ PhyPartnerAbilityGet(&cpswinst->mdio.base,
cpswinst->port[port_num -1].phy_addr,
&partnr_ablty, &gbps_partnr_ablty);
if (gbps_partnr_ablty & PHY_LINK_PARTNER_1000BT_FD) {
@@ -1281,7 +1286,7 @@ cpswif_phy_autoneg(struct cpswinst *cpswinst, u32_t
port_num, u32_t adv) {
}
/* Check if PHY link is there or not */
- if (FALSE == ((PhyLinkStatusGet(cpswinst->mdio_base,
+ if (FALSE == ((PhyLinkStatusGet(&cpswinst->mdio.base,
cpswinst->port[port_num - 1].phy_addr, 1000)))) {
LWIP_PRINTF("\n\rPHY link connectivity failed for Port %d of Inst %d.",
port_num, 0);
@@ -1319,7 +1324,7 @@ cpswif_phy_forced(struct cpswinst *cpswinst, u32_t
port_num, u32_t speed,
u32_t frc_stat_cnt = 200, frc_stat = FALSE, transfer_mode = 0;
/* Check if ethernet PHY is present or not */
- if (0 == (MDIOPhyAliveStatusGet(cpswinst->mdio_base)
+ if (0 == (MDIOPhyAliveStatusGet(&cpswinst->mdio.base)
& (1 << cpswinst->port[port_num - 1].phy_addr))){
LWIP_PRINTF("\n\rNo PHY found at addr %d for Port %d of Instance %d.",
cpswinst->port[port_num - 1].phy_addr,
@@ -1345,18 +1350,18 @@ cpswif_phy_forced(struct cpswinst *cpswinst, u32_t
port_num, u32_t speed,
return linkstat;
}
- if (FALSE == PhyReset(cpswinst->mdio_base,
+ if (FALSE == PhyReset(&cpswinst->mdio.base,
cpswinst->port[port_num - 1].phy_addr)) {
LWIP_PRINTF("\n\rPHY Reset Failed...");
return linkstat;
}
- if (TRUE == (PhyLinkStatusGet(cpswinst->mdio_base,
+ if (TRUE == (PhyLinkStatusGet(&cpswinst->mdio.base,
cpswinst->port[port_num - 1].phy_addr, 1000))) {
while (frc_stat_cnt) {
delay(50);
/* Check if PHY link is there or not */
- frc_stat = (PhyLinkStatusGet(cpswinst->mdio_base,
+ frc_stat = (PhyLinkStatusGet(&cpswinst->mdio.base,
cpswinst->port[port_num - 1].phy_addr, 1000));
if (TRUE == frc_stat) {
@@ -1372,11 +1377,11 @@ cpswif_phy_forced(struct cpswinst *cpswinst, u32_t
port_num, u32_t speed,
frc_stat_cnt = 200;
frc_stat = FALSE;
- if (PhyConfigure(cpswinst->mdio_base, cpswinst->port[port_num -1].phy_addr,
+ if (PhyConfigure(&cpswinst->mdio.base, cpswinst->port[port_num -1].phy_addr,
speed_val, duplex_val)) {
while (frc_stat_cnt) {
delay(50);
- frc_stat = PhyLinkStatusGet(cpswinst->mdio_base,
+ frc_stat = PhyLinkStatusGet(&cpswinst->mdio.base,
cpswinst->port[port_num - 1].phy_addr, 1000);
if (1 == frc_stat) {
@@ -1470,12 +1475,12 @@ cpswif_autoneg_config(u32_t inst_num, u32_t port_num) {
* Now start Autonegotiation. PHY will talk to its partner
* and give us what the partner can handle
*/
- if(PhyAutoNegotiate(cpswinst->mdio_base,
+ if(PhyAutoNegotiate(&cpswinst->mdio.base,
cpswinst->port[port_num -1].phy_addr,
&adv_val, &gig_adv_val) == TRUE) {
while(aut_neg_cnt) {
delay(50);
- auto_stat = PhyAutoNegStatusGet(cpswinst->mdio_base,
+ auto_stat = PhyAutoNegStatusGet(&cpswinst->mdio.base,
cpswinst->port[port_num -1].phy_addr);
if(TRUE == auto_stat) {
break;
@@ -1492,7 +1497,7 @@ cpswif_autoneg_config(u32_t inst_num, u32_t port_num) {
}
/* Get what the partner supports */
- PhyPartnerAbilityGet(cpswinst->mdio_base,
+ PhyPartnerAbilityGet(&cpswinst->mdio.base,
cpswinst->port[port_num -1].phy_addr,
&partnr_ablty, &gbps_partnr_ablty);
if(gbps_partnr_ablty & PHY_LINK_PARTNER_1000BT_FD) {
@@ -1789,7 +1794,7 @@ cpswif_phylink_config(struct cpswportif * cpswif, u32_t
slv_port_num) {
err_t err;
/* Check if ethernet PHY is present or not */
- if(0 == (MDIOPhyAliveStatusGet(cpswinst->mdio_base)
+ if(0 == (MDIOPhyAliveStatusGet(&cpswinst->mdio.base)
& (1 << cpswinst->port[slv_port_num - 1].phy_addr))){
LWIP_PRINTF("\n\rNo PHY found at address %d for Port %d of Instance %d.",
cpswinst->port[slv_port_num - 1].phy_addr, slv_port_num,
@@ -1808,7 +1813,7 @@ cpswif_phylink_config(struct cpswportif * cpswif, u32_t
slv_port_num) {
err = (err_t)(cpswif_autoneg_config(cpswif->inst_num, slv_port_num));
/* Check if PHY link is there or not */
- if(FALSE == ((PhyLinkStatusGet(cpswinst->mdio_base,
+ if(FALSE == ((PhyLinkStatusGet(&cpswinst->mdio.base,
cpswinst->port[slv_port_num - 1].phy_addr, 1000))))
{
LWIP_PRINTF("\n\rPHY link connectivity failed for Port %d of Instance %d.",
slv_port_num, cpswif->inst_num);
@@ -1988,7 +1993,7 @@ cpswif_inst_init(struct cpswportif *cpswif){
CPSWCPDMAReset(cpswinst->cpdma_base);
/* Initialize MDIO */
- MDIOInit(cpswinst->mdio_base, MDIO_FREQ_INPUT, MDIO_FREQ_OUTPUT);
+ MDIOInit(&cpswinst->mdio.base, MDIO_FREQ_INPUT, MDIO_FREQ_OUTPUT);
delay(1);
CPSWALEInit(cpswinst->ale_base);
@@ -2360,7 +2365,7 @@ cpswif_link_status(u32_t inst_num, u32_t slv_port_num) {
struct cpswinst *cpswinst = &cpsw_inst_data[inst_num];
- return (PhyLinkStatusGet(cpswinst->mdio_base,
+ return (PhyLinkStatusGet(&cpswinst->mdio.base,
cpswinst->port[slv_port_num - 1].phy_addr, 3));
}
diff --git a/cpsw/src/netif/mdio.c b/cpsw/src/netif/mdio.c
index 9c6c18e..9255f1d 100755
--- a/cpsw/src/netif/mdio.c
+++ b/cpsw/src/netif/mdio.c
@@ -63,7 +63,7 @@
/**
* \brief Reads a PHY register using MDIO.
*
- * \param baseAddr Base Address of the MDIO Module Registers.
+ * \param base MDIO Module Control.
* \param phyAddr PHY Adress.
* \param regNum Register Number to be read.
* \param dataPtr Pointer where the read value shall be written.
@@ -73,9 +73,10 @@
* FALSE - read is not acknowledged properly.
*
**/
-unsigned int MDIOPhyRegRead(unsigned int baseAddr, unsigned int phyAddr,
- unsigned int regNum, volatile unsigned short
*dataPtr)
+unsigned int TIMDIOPhyRegRead(mdioControl *base, unsigned int phyAddr,
+ unsigned int regNum, unsigned short *dataPtr)
{
+ uintptr_t baseAddr = ((tiMDIOControl *)base)->baseAddr;
/* Wait till transaction completion if any */
while(HWREG(baseAddr + MDIO_USERACCESS0) & MDIO_USERACCESS0_GO);
@@ -101,7 +102,7 @@ unsigned int MDIOPhyRegRead(unsigned int baseAddr, unsigned
int phyAddr,
/**
* \brief Writes a PHY register using MDIO.
*
- * \param baseAddr Base Address of the MDIO Module Registers.
+ * \param base MDIO Module Control.
* \param phyAddr PHY Adress.
* \param regNum Register Number to be read.
* \param RegVal Value to be written.
@@ -109,9 +110,10 @@ unsigned int MDIOPhyRegRead(unsigned int baseAddr,
unsigned int phyAddr,
* \return None
*
**/
-void MDIOPhyRegWrite(unsigned int baseAddr, unsigned int phyAddr,
+void TIMDIOPhyRegWrite(mdioControl *base, unsigned int phyAddr,
unsigned int regNum, unsigned short RegVal)
{
+ uintptr_t baseAddr = ((tiMDIOControl *)base)->baseAddr;
/* Wait till transaction completion if any */
while(HWREG(baseAddr + MDIO_USERACCESS0) & MDIO_USERACCESS0_GO);
@@ -129,13 +131,14 @@ void MDIOPhyRegWrite(unsigned int baseAddr, unsigned int
phyAddr,
* The bit correponding to the PHY address will be set if the PHY
* is alive.
*
- * \param baseAddr Base Address of the MDIO Module Registers.
+ * \param base MDIO Module Control.
*
* \return MDIO alive register state
*
**/
-unsigned int MDIOPhyAliveStatusGet(unsigned int baseAddr)
+unsigned int TIMDIOPhyAliveStatusGet(mdioControl *base)
{
+ uintptr_t baseAddr = ((tiMDIOControl *)base)->baseAddr;
return (HWREG(baseAddr + MDIO_ALIVE));
}
@@ -144,13 +147,14 @@ unsigned int MDIOPhyAliveStatusGet(unsigned int baseAddr)
* The bit correponding to the PHY address will be set if the PHY
* link is active.
*
- * \param baseAddr Base Address of the MDIO Module Registers.
+ * \param base MDIO Module Control.
*
* \return MDIO link register state
*
**/
-unsigned int MDIOPhyLinkStatusGet(unsigned int baseAddr)
+unsigned int TIMDIOPhyLinkStatusGet(mdioControl *base)
{
+ uintptr_t baseAddr = ((tiMDIOControl *)base)->baseAddr;
return (HWREG(baseAddr + MDIO_LINK));
}
@@ -158,15 +162,16 @@ unsigned int MDIOPhyLinkStatusGet(unsigned int baseAddr)
* \brief Initializes the MDIO peripheral. This enables the MDIO state
* machine, uses standard pre-amble and set the clock divider value.
*
- * \param baseAddr Base Address of the MDIO Module Registers.
+ * \param base MDIO Module Control.
* \param mdioInputFreq The clock input to the MDIO module
* \param mdioOutputFreq The clock output required on the MDIO bus
* \return None
*
**/
-void MDIOInit(unsigned int baseAddr, unsigned int mdioInputFreq,
+void TIMDIOInit(mdioControl *base, unsigned int mdioInputFreq,
unsigned int mdioOutputFreq)
{
+ uintptr_t baseAddr = ((tiMDIOControl *)base)->baseAddr;
unsigned int clkDiv = (mdioInputFreq/mdioOutputFreq) - 1;
HWREG(baseAddr + MDIO_CONTROL) = ((clkDiv & MDIO_CONTROL_CLKDIV)
@@ -175,35 +180,4 @@ void MDIOInit(unsigned int baseAddr, unsigned int
mdioInputFreq,
| MDIO_CONTROL_FAULTENB);
}
-/**
- * \brief Saves the MDIO register context. Note that only MDIO control
- * register context is saved here.
- *
- * \param baseAddr Base Address of the MDIO Module Registers.
- * \param contextPtr Pointer to the structure where MDIO context
- * needs to be saved.
- * \return None
- *
- **/
-void MDIOContextSave(unsigned int baseAddr, MDIOCONTEXT *contextPtr)
-{
- contextPtr->mdioCtrl = HWREG(baseAddr + MDIO_CONTROL);
-}
-
-/**
- * \brief Restores the MDIO register context. Note that only MDIO control
- * register context is restored here. Hence enough delay shall be
- * given after this API
- *
- * \param baseAddr Base Address of the MDIO Module Registers.
- * \param contextPtr Pointer to the structure where MDIO context
- * needs to be restored from
- * \return None
- *
- **/
-void MDIOContextRestore(unsigned int baseAddr, MDIOCONTEXT *contextPtr)
-{
- HWREG(baseAddr + MDIO_CONTROL) = contextPtr->mdioCtrl;
-}
-
/***************************** End Of File ***********************************/
diff --git a/cpsw/src/netif/phy.c b/cpsw/src/netif/phy.c
index 1ce9494..cc032cb 100755
--- a/cpsw/src/netif/phy.c
+++ b/cpsw/src/netif/phy.c
@@ -53,25 +53,25 @@
/**
* \brief Reads the PHY ID.
*
- * \param mdioBaseAddr Base Address of the MDIO Module Registers.
+ * \param mdio MDIO Module Control.
* \param phyAddr PHY Adress.
*
* \return 32 bit PHY ID (ID1:ID2)
*
**/
-unsigned int PhyIDGet(unsigned int mdioBaseAddr, unsigned int phyAddr)
+unsigned int PhyIDGet(mdioControl *mdio, unsigned int phyAddr)
{
unsigned int id = 0;
unsigned short data;
/* read the ID1 register */
- MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_ID1, &data);
+ MDIOPhyRegRead(mdio, phyAddr, PHY_ID1, &data);
/* update the ID1 value */
id = data << PHY_ID_SHIFT;
/* read the ID2 register */
- MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_ID2, &data);
+ MDIOPhyRegRead(mdio, phyAddr, PHY_ID2, &data);
/* update the ID2 value */
id |= data;
@@ -83,7 +83,7 @@ unsigned int PhyIDGet(unsigned int mdioBaseAddr, unsigned int
phyAddr)
/**
* \brief Reads a register from the the PHY
*
- * \param mdioBaseAddr Base Address of the MDIO Module Registers.
+ * \param mdio MDIO Module Control.
* \param phyAddr PHY Adress.
* \param regIdx Index of the register to be read
* \param regValAdr address where value of the register will be written
@@ -91,16 +91,16 @@ unsigned int PhyIDGet(unsigned int mdioBaseAddr, unsigned
int phyAddr)
* \return status of the read
*
**/
-unsigned int PhyRegRead(unsigned int mdioBaseAddr, unsigned int phyAddr,
+unsigned int PhyRegRead(mdioControl *mdio, unsigned int phyAddr,
unsigned int regIdx, unsigned short *regValAdr)
{
- return (MDIOPhyRegRead(mdioBaseAddr, phyAddr, regIdx, regValAdr));
+ return (MDIOPhyRegRead(mdio, phyAddr, regIdx, regValAdr));
}
/**
* \brief Writes a register with the input
*
- * \param mdioBaseAddr Base Address of the MDIO Module Registers.
+ * \param mdio MDIO Module Control.
* \param phyAddr PHY Adress.
* \param regIdx Index of the register to be read
* \param regValAdr value to be written
@@ -108,16 +108,16 @@ unsigned int PhyRegRead(unsigned int mdioBaseAddr,
unsigned int phyAddr,
* \return None
*
**/
-void PhyRegWrite(unsigned int mdioBaseAddr, unsigned int phyAddr,
+void PhyRegWrite(mdioControl *mdio, unsigned int phyAddr,
unsigned int regIdx, unsigned short regVal)
{
- MDIOPhyRegWrite(mdioBaseAddr, phyAddr, regIdx, regVal);
+ MDIOPhyRegWrite(mdio, phyAddr, regIdx, regVal);
}
/**
* \brief Enables Loop Back mode
*
- * \param mdioBaseAddr Base Address of the MDIO Module Registers.
+ * \param mdio MDIO Module Control.
* \param phyAddr PHY Adress.
*
* \return status after enabling. \n
@@ -125,11 +125,11 @@ void PhyRegWrite(unsigned int mdioBaseAddr, unsigned int
phyAddr,
* FALSE if not able to enable
*
**/
-unsigned int PhyLoopBackEnable(unsigned int mdioBaseAddr, unsigned int phyAddr)
+unsigned int PhyLoopBackEnable(mdioControl *mdio, unsigned int phyAddr)
{
unsigned short data;
- if(MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BCR, &data) != TRUE )
+ if(MDIOPhyRegRead(mdio, phyAddr, PHY_BCR, &data) != TRUE )
{
return FALSE;
}
@@ -137,7 +137,7 @@ unsigned int PhyLoopBackEnable(unsigned int mdioBaseAddr,
unsigned int phyAddr)
data |= PHY_LPBK_ENABLE;
/* Enable loop back */
- MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BCR, data);
+ MDIOPhyRegWrite(mdio, phyAddr, PHY_BCR, data);
return TRUE;
}
@@ -145,7 +145,7 @@ unsigned int PhyLoopBackEnable(unsigned int mdioBaseAddr,
unsigned int phyAddr)
/**
* \brief Disables Loop Back mode
*
- * \param mdioBaseAddr Base Address of the MDIO Module Registers.
+ * \param mdio MDIO Module Control.
* \param phyAddr PHY Adress.
*
* \return status after enabling. \n
@@ -153,11 +153,11 @@ unsigned int PhyLoopBackEnable(unsigned int mdioBaseAddr,
unsigned int phyAddr)
* FALSE if not able to disable
*
**/
-unsigned int PhyLoopBackDisable(unsigned int mdioBaseAddr, unsigned int
phyAddr)
+unsigned int PhyLoopBackDisable(mdioControl *mdio, unsigned int phyAddr)
{
unsigned short data;
- if(MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BCR, &data) != TRUE )
+ if(MDIOPhyRegRead(mdio, phyAddr, PHY_BCR, &data) != TRUE )
{
return FALSE;
}
@@ -165,7 +165,7 @@ unsigned int PhyLoopBackDisable(unsigned int mdioBaseAddr,
unsigned int phyAddr)
data &= ~(PHY_LPBK_ENABLE);
/* Disable loop back */
- MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BCR, data);
+ MDIOPhyRegWrite(mdio, phyAddr, PHY_BCR, data);
return TRUE;
}
@@ -173,7 +173,7 @@ unsigned int PhyLoopBackDisable(unsigned int mdioBaseAddr,
unsigned int phyAddr)
/**
* \brief Resets the PHY
*
- * \param mdioBaseAddr Base Address of the MDIO Module Registers.
+ * \param mdio MDIO Module Control.
* \param phyAddr PHY Adress.
* \param speed Speed to be enabled
* \param duplexMode Duplex Mode
@@ -183,20 +183,20 @@ unsigned int PhyLoopBackDisable(unsigned int
mdioBaseAddr, unsigned int phyAddr)
* FALSE if configuration failed
*
**/
-unsigned int PhyReset(unsigned int mdioBaseAddr, unsigned int phyAddr)
+unsigned int PhyReset(mdioControl *mdio, unsigned int phyAddr)
{
unsigned short data;
data = PHY_SOFTRESET;
/* Reset the phy */
- MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BCR, data);
+ MDIOPhyRegWrite(mdio, phyAddr, PHY_BCR, data);
/* wait till the reset bit is auto cleared */
while(data & PHY_SOFTRESET)
{
/* Read the reset */
- if(MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BCR, &data) != TRUE)
+ if(MDIOPhyRegRead(mdio, phyAddr, PHY_BCR, &data) != TRUE)
{
return FALSE;
}
@@ -208,7 +208,7 @@ unsigned int PhyReset(unsigned int mdioBaseAddr, unsigned
int phyAddr)
/**
* \brief Configures the PHY for a given speed and duplex mode.
*
- * \param mdioBaseAddr Base Address of the MDIO Module Registers.
+ * \param mdio MDIO Module Control.
* \param phyAddr PHY Adress.
* \param speed Speed to be enabled
* \param duplexMode Duplex Mode
@@ -218,11 +218,11 @@ unsigned int PhyReset(unsigned int mdioBaseAddr, unsigned
int phyAddr)
* FALSE if configuration failed
*
**/
-unsigned int PhyConfigure(unsigned int mdioBaseAddr, unsigned int phyAddr,
+unsigned int PhyConfigure(mdioControl *mdio, unsigned int phyAddr,
unsigned short speed, unsigned short duplexMode)
{
/* Set the configurations */
- MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BCR, (speed | duplexMode));
+ MDIOPhyRegWrite(mdio, phyAddr, PHY_BCR, (speed | duplexMode));
return TRUE;
}
@@ -231,7 +231,7 @@ unsigned int PhyConfigure(unsigned int mdioBaseAddr,
unsigned int phyAddr,
* \brief This function ask the phy device to start auto negotiation.
*
*
- * \param mdioBaseAddr Base Address of the MDIO Module Registers.
+ * \param mdio MDIO Module Control.
* \param phyAddr PHY Adress.
* \param advVal Autonegotiation advertisement value
* \param gigAdvVal Gigabit capability advertisement value
@@ -252,13 +252,13 @@ unsigned int PhyConfigure(unsigned int mdioBaseAddr,
unsigned int phyAddr,
* FALSE if autonegotiation not started
*
**/
-unsigned int PhyAutoNegotiate(unsigned int mdioBaseAddr, unsigned int phyAddr,
+unsigned int PhyAutoNegotiate(mdioControl *mdio, unsigned int phyAddr,
unsigned short *advPtr, unsigned short
*gigAdvPtr)
{
- volatile unsigned short data;
- volatile unsigned short anar;
+ unsigned short data;
+ unsigned short anar;
- if(MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BCR, &data) != TRUE )
+ if(MDIOPhyRegRead(mdio, phyAddr, PHY_BCR, &data) != TRUE )
{
return FALSE;
}
@@ -273,29 +273,29 @@ unsigned int PhyAutoNegotiate(unsigned int mdioBaseAddr,
unsigned int phyAddr,
}
/* Enable Auto Negotiation */
- MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BCR, data);
+ MDIOPhyRegWrite(mdio, phyAddr, PHY_BCR, data);
- if(MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BCR, &data) != TRUE )
+ if(MDIOPhyRegRead(mdio, phyAddr, PHY_BCR, &data) != TRUE )
{
return FALSE;
}
/* Write Auto Negotiation capabilities */
- MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_AUTONEG_ADV, &anar);
+ MDIOPhyRegRead(mdio, phyAddr, PHY_AUTONEG_ADV, &anar);
anar &= ~PHY_ADV_VAL_MASK;
- MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_AUTONEG_ADV, (anar |(*advPtr)));
+ MDIOPhyRegWrite(mdio, phyAddr, PHY_AUTONEG_ADV, (anar |(*advPtr)));
/* Write Auto Negotiation Gigabyte capabilities */
anar = 0;
- MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_1000BT_CONTROL, &anar);
+ MDIOPhyRegRead(mdio, phyAddr, PHY_1000BT_CONTROL, &anar);
anar &= ~PHY_GIG_ADV_VAL_MASK;
- MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_1000BT_CONTROL,
+ MDIOPhyRegWrite(mdio, phyAddr, PHY_1000BT_CONTROL,
(anar |(*gigAdvPtr)));
data |= PHY_AUTONEG_RESTART;
/* Start Auto Negotiation */
- MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BCR, data);
+ MDIOPhyRegWrite(mdio, phyAddr, PHY_BCR, data);
return TRUE;
}
@@ -303,18 +303,18 @@ unsigned int PhyAutoNegotiate(unsigned int mdioBaseAddr,
unsigned int phyAddr,
/**
* \brief Returns the status of Auto Negotiation completion.
*
- * \param mdioBaseAddr Base Address of the MDIO Module Registers.
+ * \param mdio MDIO Module Control.
* \param phyAddr PHY Adress.
*
* \return Auto negotiation completion status \n
* TRUE if auto negotiation is completed
* FALSE if auto negotiation is not completed
**/
-unsigned int PhyAutoNegStatusGet(unsigned int mdioBaseAddr, unsigned int
phyAddr)
+unsigned int PhyAutoNegStatusGet(mdioControl *mdio, unsigned int phyAddr)
{
- volatile unsigned short data;
+ unsigned short data;
- MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BSR, &data);
+ MDIOPhyRegRead(mdio, phyAddr, PHY_BSR, &data);
/* Auto negotiation completion status */
if(PHY_AUTONEG_COMPLETE == (data & (PHY_AUTONEG_STATUS)))
@@ -328,7 +328,7 @@ unsigned int PhyAutoNegStatusGet(unsigned int mdioBaseAddr,
unsigned int phyAddr
/**
* \brief Reads the Link Partner Ability register of the PHY.
*
- * \param mdioBaseAddr Base Address of the MDIO Module Registers.
+ * \param mdio MDIO Module Control.
* \param phyAddr PHY Adress.
* \param ptnerAblty Pointer to which partner ability will be written.
* \param gbpsPtnerAblty Pointer to which Giga bit capability will be
written.
@@ -343,19 +343,19 @@ unsigned int PhyAutoNegStatusGet(unsigned int
mdioBaseAddr, unsigned int phyAddr
* TRUE if reading successful
* FALSE if reading failed
**/
-unsigned int PhyPartnerAbilityGet(unsigned int mdioBaseAddr,
+unsigned int PhyPartnerAbilityGet(mdioControl *mdio,
unsigned int phyAddr,
unsigned short *ptnerAblty,
unsigned short *gbpsPtnerAblty)
{
unsigned int status;
- status = MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_LINK_PARTNER_ABLTY,
+ status = MDIOPhyRegRead(mdio, phyAddr, PHY_LINK_PARTNER_ABLTY,
ptnerAblty);
if (*gbpsPtnerAblty != 0)
{
- status = status | MDIOPhyRegRead(mdioBaseAddr, phyAddr,
PHY_1000BT_STATUS,
+ status = status | MDIOPhyRegRead(mdio, phyAddr, PHY_1000BT_STATUS,
gbpsPtnerAblty);
}
@@ -365,7 +365,7 @@ unsigned int PhyPartnerAbilityGet(unsigned int mdioBaseAddr,
/**
* \brief Reads the link status of the PHY.
*
- * \param mdioBaseAddr Base Address of the MDIO Module Registers.
+ * \param mdio MDIO Module Control.
* \param phyAddr PHY Adress.
* \param retries The number of retries before indicating down status
*
@@ -376,17 +376,17 @@ unsigned int PhyPartnerAbilityGet(unsigned int
mdioBaseAddr,
* \note This reads both the basic status register of the PHY and the
* link register of MDIO for double check
**/
-unsigned int PhyLinkStatusGet(unsigned int mdioBaseAddr,
+unsigned int PhyLinkStatusGet(mdioControl *mdio,
unsigned int phyAddr,
- volatile unsigned int retries)
+ unsigned int retries)
{
- volatile unsigned short linkStatus;
+ unsigned short linkStatus;
retries++;
while (retries)
{
/* First read the BSR of the PHY */
- MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BSR, &linkStatus);
+ MDIOPhyRegRead(mdio, phyAddr, PHY_BSR, &linkStatus);
if(linkStatus & PHY_LINK_STATUS)
{
diff --git a/uLan/ports/driver/tms570_emac/phy_dp83848h.c
b/uLan/ports/driver/tms570_emac/phy_dp83848h.c
index 91516bf..36c1b61 100644
--- a/uLan/ports/driver/tms570_emac/phy_dp83848h.c
+++ b/uLan/ports/driver/tms570_emac/phy_dp83848h.c
@@ -32,7 +32,9 @@
*
*/
+#ifndef __rtems__
#include "ti_drv_mdio.h"
+#endif /* __rtems__ */
#include "phy_dp83848h.h"
#ifdef __rtems__
#include "mdio.h"
@@ -54,53 +56,53 @@
#endif
void
-PHY_reset(volatile tms570_mdio_t *mdioBaseAddr, uint32_t phyAddr)
+PHY_reset(mdioControl *mdio, uint32_t phyAddr)
{
- volatile unsigned short regContent;
+ unsigned short regContent;
- MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BMCR, PHY_RESET_m);
- while (MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BMCR, ®Content) &
PHY_RESET_m);
+ MDIOPhyRegWrite(mdio, phyAddr, PHY_BMCR, PHY_RESET_m);
+ while (MDIOPhyRegRead(mdio, phyAddr, PHY_BMCR, ®Content) & PHY_RESET_m);
}
uint32_t
-PHY_partner_ability_get(volatile tms570_mdio_t *mdioBaseAddr, uint32_t
phyAddr, unsigned short *regContent)
+PHY_partner_ability_get(mdioControl *mdio, uint32_t phyAddr, unsigned short
*regContent)
{
- return (MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_ANLPAR, regContent));
+ return (MDIOPhyRegRead(mdio, phyAddr, PHY_ANLPAR, regContent));
}
uint32_t
-PHY_start_auto_negotiate(volatile tms570_mdio_t *mdioBaseAddr, uint32_t
phyAddr, unsigned short advVal)
+PHY_start_auto_negotiate(mdioControl *mdio, uint32_t phyAddr, unsigned short
advVal)
{
- volatile unsigned short regContent = 0;
+ unsigned short regContent = 0;
/* Enable Auto Negotiation */
- if (MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BMCR, ®Content) != TRUE) {
+ if (MDIOPhyRegRead(mdio, phyAddr, PHY_BMCR, ®Content) != TRUE) {
return FALSE;
}
regContent |= PHY_AUTONEG_EN_m;
- MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BMCR, regContent); /*
originally ...HY_BMCR, PHY_RESET_m | PHY_AUTONEG_EN_m); */
+ MDIOPhyRegWrite(mdio, phyAddr, PHY_BMCR, regContent); /* originally
...HY_BMCR, PHY_RESET_m | PHY_AUTONEG_EN_m); */
/* Write Auto Negotiation capabilities */
- if (MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_ANAR, ®Content) != TRUE) {
+ if (MDIOPhyRegRead(mdio, phyAddr, PHY_ANAR, ®Content) != TRUE) {
return FALSE;
}
regContent |= advVal;
- MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_ANAR, regContent);
+ MDIOPhyRegWrite(mdio, phyAddr, PHY_ANAR, regContent);
/* Start Auto Negotiation */
- MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BMCR, ®Content);
+ MDIOPhyRegRead(mdio, phyAddr, PHY_BMCR, ®Content);
regContent |= PHY_AUTONEG_REST;
- MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BMCR, regContent);
+ MDIOPhyRegWrite(mdio, phyAddr, PHY_BMCR, regContent);
return TRUE; /* request to PHY through EMAC for autonegotiation
established */
}
uint32_t
-PHY_is_done_auto_negotiate(volatile tms570_mdio_t *mdioBaseAddr, uint32_t
phyAddr)
+PHY_is_done_auto_negotiate(mdioControl *mdio, uint32_t phyAddr)
{
- volatile unsigned short regContent;
+ unsigned short regContent;
- if (MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BMSR, ®Content) != TRUE) {
+ if (MDIOPhyRegRead(mdio, phyAddr, PHY_BMSR, ®Content) != TRUE) {
return FALSE;
}
if ((regContent & PHY_A_NEG_COMPLETE_m) == 0)
@@ -109,25 +111,25 @@ PHY_is_done_auto_negotiate(volatile tms570_mdio_t
*mdioBaseAddr, uint32_t phyAdd
}
uint32_t
-PHY_auto_negotiate(volatile tms570_mdio_t *mdioBaseAddr, uint32_t phyAddr,
unsigned short advVal)
+PHY_auto_negotiate(mdioControl *mdio, uint32_t phyAddr, unsigned short advVal)
{
- if (PHY_start_auto_negotiate(mdioBaseAddr, phyAddr, advVal) == FALSE)
+ if (PHY_start_auto_negotiate(mdio, phyAddr, advVal) == FALSE)
return FALSE;
- while (PHY_is_done_auto_negotiate(mdioBaseAddr, phyAddr) == FALSE);
+ while (PHY_is_done_auto_negotiate(mdio, phyAddr) == FALSE);
return TRUE;
}
uint32_t
-PHY_link_status_get(volatile tms570_mdio_t *mdioBaseAddr, uint32_t phyAddr,
volatile uint32_t retries)
+PHY_link_status_get(mdioControl *mdio, uint32_t phyAddr, uint32_t retries)
{
- volatile unsigned short linkStatus;
- volatile uint32_t retVal = TRUE;
+ unsigned short linkStatus;
+ uint32_t retVal = TRUE;
while (retVal == TRUE) {
/* Read the BSR of the PHY */
- MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BMSR, &linkStatus);
+ MDIOPhyRegRead(mdio, phyAddr, PHY_BMSR, &linkStatus);
if (linkStatus & PHY_LINK_STATUS_m) {
break;
@@ -141,42 +143,42 @@ PHY_link_status_get(volatile tms570_mdio_t *mdioBaseAddr,
uint32_t phyAddr, vola
}
uint32_t
-PHY_RMII_mode_get(volatile tms570_mdio_t *mdioBaseAddr, uint32_t phyAddr)
+PHY_RMII_mode_get(mdioControl *mdio, uint32_t phyAddr)
{
- volatile unsigned short regContent;
+ unsigned short regContent;
/* Read the RBR of the PHY */
- MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_RBR, ®Content);
+ MDIOPhyRegRead(mdio, phyAddr, PHY_RBR, ®Content);
return (regContent & PHY_RMII_MODE);
}
void
-PHY_MII_mode_set(volatile tms570_mdio_t *mdioBaseAddr, uint32_t phyAddr,
uint32_t mode)
+PHY_MII_mode_set(mdioControl *mdio, uint32_t phyAddr, uint32_t mode)
{
- volatile unsigned short regContent;
+ unsigned short regContent;
/* Read the RBR of the PHY */
- MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_RBR, ®Content);
+ MDIOPhyRegRead(mdio, phyAddr, PHY_RBR, ®Content);
/* Write the RBR of the PHY */
regContent &= 0x1f;
regContent |= ( mode << 5 );
- MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_RBR, regContent);
+ MDIOPhyRegWrite(mdio, phyAddr, PHY_RBR, regContent);
}
void
-PHY_Power_Down(volatile tms570_mdio_t *mdioBaseAddr, uint32_t phyAddr)
+PHY_Power_Down(mdioControl *mdio, uint32_t phyAddr)
{
- volatile unsigned short regContent;
+ unsigned short regContent;
- MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BMCR, ®Content);
- MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BMCR, regContent |
PHY_POWERDOWN_m);
+ MDIOPhyRegRead(mdio, phyAddr, PHY_BMCR, ®Content);
+ MDIOPhyRegWrite(mdio, phyAddr, PHY_BMCR, regContent | PHY_POWERDOWN_m);
}
void
-PHY_Power_Up(volatile tms570_mdio_t *mdioBaseAddr, uint32_t phyAddr)
+PHY_Power_Up(mdioControl *mdio, uint32_t phyAddr)
{
- volatile unsigned short regContent;
+ unsigned short regContent;
- MDIOPhyRegRead(mdioBaseAddr, phyAddr, PHY_BMCR, ®Content);
- MDIOPhyRegWrite(mdioBaseAddr, phyAddr, PHY_BMCR, regContent &
~PHY_POWERDOWN_m);
+ MDIOPhyRegRead(mdio, phyAddr, PHY_BMCR, ®Content);
+ MDIOPhyRegWrite(mdio, phyAddr, PHY_BMCR, regContent & ~PHY_POWERDOWN_m);
}
diff --git a/uLan/ports/driver/tms570_emac/phy_dp83848h.h
b/uLan/ports/driver/tms570_emac/phy_dp83848h.h
index d45ecc5..2c22905 100644
--- a/uLan/ports/driver/tms570_emac/phy_dp83848h.h
+++ b/uLan/ports/driver/tms570_emac/phy_dp83848h.h
@@ -35,9 +35,9 @@
#ifndef __DRV_PHY_H
#define __DRV_PHY_H
-#ifdef __rtems__
-#include <bsp/ti_herc/reg_mdio.h>
-#endif /* __rtems__ */
+#include "mdio.h"
+
+#include <stdint.h>
#ifdef __cplusplus
extern "C" {
@@ -106,7 +106,7 @@ extern "C" {
* This must be implemented in the layer above.
* @note Calling this function is blocking until PHY
indicates the reset process is complete.
*/
-void PHY_reset(volatile tms570_mdio_t *mdioBaseAddr, uint32_t phyAddr);
+void PHY_reset(mdioControl *mdio, uint32_t phyAddr);
/**
* Reads link partner ability register from the PHY
@@ -117,7 +117,7 @@ void PHY_reset(volatile tms570_mdio_t *mdioBaseAddr,
uint32_t phyAddr);
*
* @return TRUE if reading succesful, FALSE if reading failed
*/
-uint32_t PHY_partner_ability_get(volatile tms570_mdio_t *mdioBaseAddr,
uint32_t phyAddr, unsigned short *regContent);
+uint32_t PHY_partner_ability_get(mdioControl *mdio, uint32_t phyAddr, unsigned
short *regContent);
/**
* This function does Autonegotiates with the EMAC device connected
@@ -136,7 +136,7 @@ uint32_t PHY_partner_ability_get(volatile tms570_mdio_t
*mdioBaseAddr, uint32_t
*
* @note this function is blocking, waits till link is established
*/
-uint32_t PHY_auto_negotiate(volatile tms570_mdio_t *mdioBaseAddr, uint32_t
phyAddr, unsigned short advVal);
+uint32_t PHY_auto_negotiate(mdioControl *mdio, uint32_t phyAddr, unsigned
short advVal);
/**
* This function starts autonegotiaon with the EMAC device connected
@@ -155,7 +155,7 @@ uint32_t PHY_auto_negotiate(volatile tms570_mdio_t
*mdioBaseAddr, uint32_t phyAd
* @return TRUE if setting autonegotiation startup succesful,
* FALSE if starting autonegotiation failed
*/
-uint32_t PHY_start_auto_negotiate(volatile tms570_mdio_t *mdioBaseAddr,
uint32_t phyAddr, unsigned short advVal);
+uint32_t PHY_start_auto_negotiate(mdioControl *mdio, uint32_t phyAddr,
unsigned short advVal);
/**
* This function examines, whether autonegotiation is done.
@@ -166,7 +166,7 @@ uint32_t PHY_start_auto_negotiate(volatile tms570_mdio_t
*mdioBaseAddr, uint32_t
*
* @return TRUE if autonegotiation succesfull and done, FALSE if
autonegotiation failed.
*/
-uint32_t PHY_is_done_auto_negotiate(volatile tms570_mdio_t *mdioBaseAddr,
uint32_t phyAddr);
+uint32_t PHY_is_done_auto_negotiate(mdioControl *mdio, uint32_t phyAddr);
/**
* Reads the link status of the PHY.
@@ -182,7 +182,7 @@ uint32_t PHY_is_done_auto_negotiate(volatile tms570_mdio_t
*mdioBaseAddr, uint32
* @note This reads both the basic status register of the PHY and the
* link register of MDIO for double check
**/
-uint32_t PHY_link_status_get(volatile tms570_mdio_t *mdioBaseAddr, uint32_t
phyAddr, volatile uint32_t retries);
+uint32_t PHY_link_status_get(mdioControl *mdio, uint32_t phyAddr, volatile
uint32_t retries);
/**
* Fetches RMII/MII mode of PHY.
@@ -193,7 +193,7 @@ uint32_t PHY_link_status_get(volatile tms570_mdio_t
*mdioBaseAddr, uint32_t phyA
* @return TRUE if mode of PHY is set to RMII \
* FALSE if mode of PHY is set to MII
*/
-uint32_t PHY_RMII_mode_get(volatile tms570_mdio_t *mdioBaseAddr, uint32_t
phyAddr);
+uint32_t PHY_RMII_mode_get(mdioControl *mdio, uint32_t phyAddr);
/**
* Sets RMII/MII mode of PHY.
@@ -204,7 +204,7 @@ uint32_t PHY_RMII_mode_get(volatile tms570_mdio_t
*mdioBaseAddr, uint32_t phyAdd
* 1 - RMII \
* 0 - MII
*/
-void PHY_MII_mode_set(volatile tms570_mdio_t *mdioBaseAddr, uint32_t phyAddr,
uint32_t mode);
+void PHY_MII_mode_set(mdioControl *mdio, uint32_t phyAddr, uint32_t mode);
/**
* Powers down the PHY.
@@ -212,7 +212,7 @@ void PHY_MII_mode_set(volatile tms570_mdio_t *mdioBaseAddr,
uint32_t phyAddr, ui
* @param mdioBaseAddr Base Address of the MDIO Module Registers.
* @param phyAddr PHY Address (0-31).
*/
-void PHY_Power_Down(volatile tms570_mdio_t *mdioBaseAddr, uint32_t phyAddr);
+void PHY_Power_Down(mdioControl *mdio, uint32_t phyAddr);
/**
@@ -221,7 +221,7 @@ void PHY_Power_Down(volatile tms570_mdio_t *mdioBaseAddr,
uint32_t phyAddr);
* @param mdioBaseAddr Base Address of the MDIO Module Registers.
* @param phyAddr PHY Address (0-31).
*/
-void PHY_Power_Up(volatile tms570_mdio_t *mdioBaseAddr, uint32_t phyAddr);
+void PHY_Power_Up(mdioControl *mdio, uint32_t phyAddr);
#ifdef __cplusplus
}
diff --git a/uLan/ports/driver/tms570_emac/ti_drv_mdio.h
b/uLan/ports/driver/tms570_emac/ti_drv_mdio.h
deleted file mode 100644
index e17046c..0000000
--- a/uLan/ports/driver/tms570_emac/ti_drv_mdio.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
-* Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com
-*
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the
-* distribution.
-*
-* Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*
-*/
-
-#if 0
-#ifndef __MDIO_H__
-#define __MDIO_H__
-
-#include <bsp/tms570.h>
-#include <stdbool.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/*****************************************************************************/
-/**
- * \brief Reads a PHY register using MDIO.
- *
- * \param baseAddr Base Address of the MDIO Module Registers.
- * \param phyAddr PHY Adress.
- * \param regNum Register Number to be read.
- * \param dataPtr Pointer where the read value shall be written.
- *
- * \return status of the read \n
- * TRUE - read is successful.\n
- * FALSE - read is not acknowledged properly.
- *
- **/
-
-static inline uint32_t
-MDIOPhyRegRead(volatile tms570_mdio_t *baseAddr, uint32_t phyAddr,
- uint32_t regNum, volatile unsigned short *dataPtr)
-{
- /* Wait till transaction completion if any */
- while (baseAddr->USERACCESS0 & TMS570_MDIO_USERACCESS0_GO);
-
- baseAddr->USERACCESS0
- = (TMS570_MDIO_USERACCESS0_GO
- |TMS570_MDIO_USERACCESS0_REGADR(regNum)
- |TMS570_MDIO_USERACCESS0_PHYADR(phyAddr));
-
- /* wait for command completion */
- while (baseAddr->USERACCESS0 & TMS570_MDIO_USERACCESS0_GO);
-
- /* Store the data if the read is acknowledged */
- if (baseAddr->USERACCESS0 & TMS570_MDIO_USERACCESS0_ACK) {
- *dataPtr = (unsigned
short)TMS570_MDIO_USERACCESS0_DATA_GET(baseAddr->USERACCESS0);
- return true;
- }
-
- return false;
-}
-
-/**
- * \brief Writes a PHY register using MDIO.
- *
- * \param baseAddr Base Address of the MDIO Module Registers.
- * \param phyAddr PHY Adress.
- * \param regNum Register Number to be read.
- * \param RegVal Value to be written.
- *
- * \return None
- *
- **/
-static inline void
-MDIOPhyRegWrite(volatile tms570_mdio_t *baseAddr, uint32_t phyAddr,
- uint32_t regNum, unsigned short RegVal)
-{
- /* Wait till transaction completion if any */
- while (baseAddr->USERACCESS0 & TMS570_MDIO_USERACCESS0_GO);
-
- baseAddr->USERACCESS0 =
- (TMS570_MDIO_USERACCESS0_WRITE
- | TMS570_MDIO_USERACCESS0_GO
- |TMS570_MDIO_USERACCESS0_REGADR(regNum)
- |TMS570_MDIO_USERACCESS0_PHYADR(phyAddr)
- | RegVal);
-
- /* wait for command completion*/
- while (baseAddr->USERACCESS0 & TMS570_MDIO_USERACCESS0_GO);
-}
-/**
- * \brief Reads the alive status of all PHY connected to this MDIO.
- * The bit correponding to the PHY address will be set if the PHY
- * is alive.
- *
- * \param baseAddr Base Address of the MDIO Module Registers.
- *
- * \return MDIO alive register state
- *
- **/
-static inline uint32_t
-MDIOPhyAliveStatusGet(volatile tms570_mdio_t *baseAddr)
-{
- return (baseAddr->ALIVE);
-}
-
-/**
- * \brief Reads the link status of all PHY connected to this MDIO.
- * The bit correponding to the PHY address will be set if the PHY
- * link is active.
- *
- * \param baseAddr Base Address of the MDIO Module Registers.
- *
- * \return MDIO link register state
- *
- **/
-static inline uint32_t
-MDIOPhyLinkStatusGet(volatile tms570_mdio_t *baseAddr)
-{
- return (baseAddr->LINK);
-}
-
-/**
- * \brief Initializes the MDIO peripheral. This enables the MDIO state
- * machine, uses standard pre-amble and set the clock divider value.
- *
- * \param baseAddr Base Address of the MDIO Module Registers.
- * \param mdioInputFreq The clock input to the MDIO module
- * \param mdioOutputFreq The clock output required on the MDIO bus
- * \return None
- *
- **/
-static inline void
-MDIOInit(volatile tms570_mdio_t *baseAddr, uint32_t mdioInputFreq,
- uint32_t mdioOutputFreq)
-{
- baseAddr->CONTROL = TMS570_MDIO_CONTROL_HIGHEST_USER_CHANNEL(1) |
- TMS570_MDIO_CONTROL_ENABLE |
- TMS570_MDIO_CONTROL_CLKDIV(0x60);
-}
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* __MDIO_H__ */
-#endif /* 0 */
diff --git a/uLan/ports/driver/tms570_emac/tms570_emac.h
b/uLan/ports/driver/tms570_emac/tms570_emac.h
index 26993e9..1d0174e 100644
--- a/uLan/ports/driver/tms570_emac/tms570_emac.h
+++ b/uLan/ports/driver/tms570_emac/tms570_emac.h
@@ -5,6 +5,7 @@
#include "netif/etharp.h"
#include "lwip/sys.h"
#include "bsp/tms570.h"
+#include "hw_mdio.h"
/*to rtems*/
#define EMAC_CTRL_RAM_BASE (0xFC520000U)
@@ -93,8 +94,8 @@ struct tms570_netif_state {
volatile tms570_emacc_t *emac_ctrl_base;
volatile u32_t emac_ctrl_ram;
- /* MDIO base address */
- volatile tms570_mdio_t *mdio_base;
+ /* MDIO module control */
+ tiMDIOControl mdio;
/* The RX/TX channel 0 state description
* (keeps track of used/freed Buffer Descriptors)
diff --git a/uLan/ports/driver/tms570_emac/tms570_netif.c
b/uLan/ports/driver/tms570_emac/tms570_netif.c
index 8d14687..74758e5 100644
--- a/uLan/ports/driver/tms570_emac/tms570_netif.c
+++ b/uLan/ports/driver/tms570_emac/tms570_netif.c
@@ -57,7 +57,6 @@
#include "eth_lwip.h"
#include "tms570_netif.h"
#include "ti_drv_emac.h"
-#include "ti_drv_mdio.h"
#include "phy_dp83848h.h"
#include "tms570_emac.h"
@@ -162,7 +161,12 @@ tms570_eth_init_state(void)
nf_state->emac_base = &TMS570_EMACM;
nf_state->emac_ctrl_base = &TMS570_EMACC;
nf_state->emac_ctrl_ram = EMAC_CTRL_RAM_BASE;
- nf_state->mdio_base = &TMS570_MDIO;
+ nf_state->mdio.base.init = TIMDIOInit;
+ nf_state->mdio.base.phyAliveStatusGet = TIMDIOPhyAliveStatusGet;
+ nf_state->mdio.base.phyLinkStatusGet = TIMDIOPhyLinkStatusGet;
+ nf_state->mdio.base.phyRegRead = TIMDIOPhyRegRead;
+ nf_state->mdio.base.phyRegWrite = TIMDIOPhyRegWrite;
+ nf_state->mdio.baseAddr = (uintptr_t) &TMS570_MDIO;
nf_state->phy_addr = DEFAULT_PHY_ADDR;
#if !NO_SYS
nf_state->waitTicksForPHYAneg = TICKS_PHY_AUTONEG;
@@ -293,8 +297,8 @@ tms570_eth_init_find_PHY(struct tms570_netif_state
*nf_state)
uint16_t regContent;
uint32_t physAlive;
- MDIOPhyRegRead(nf_state->mdio_base, nf_state->phy_addr, PHY_BMSR,
®Content);
- physAlive = MDIOPhyAliveStatusGet(nf_state->mdio_base);
+ MDIOPhyRegRead(&nf_state->mdio.base, nf_state->phy_addr, PHY_BMSR,
®Content);
+ physAlive = MDIOPhyAliveStatusGet(&nf_state->mdio.base);
/* Find first alive PHY -- or use default if alive */
if (!(physAlive & (1 << nf_state->phy_addr))) {
for (index = 0; index < NUM_OF_PHYs; index++) {
@@ -307,11 +311,11 @@ tms570_eth_init_find_PHY(struct tms570_netif_state
*nf_state)
* reading random register, making MDIO set
* alive bit for current PHY
*/
- MDIOPhyRegRead(nf_state->mdio_base, index,
+ MDIOPhyRegRead(&nf_state->mdio.base, index,
PHY_BMCR, ®Content);
/* Get updated register */
- physAlive = MDIOPhyAliveStatusGet(nf_state->mdio_base);
+ physAlive = MDIOPhyAliveStatusGet(&nf_state->mdio.base);
if (physAlive & (1 << index)) {
nf_state->phy_addr = index;
break;
@@ -368,7 +372,7 @@ tms570_eth_init_hw(struct tms570_netif_state *nf_state)
/* Initialize EMAC control module and EMAC module */
EMACInit(nf_state->emac_ctrl_base, nf_state->emac_base);
/* Initialize MDIO module (reset) */
- MDIOInit(nf_state->mdio_base, 0x0, 0x0);
+ MDIOInit(&nf_state->mdio.base, 0x0, 0x0);
if ((retVal = tms570_eth_init_find_PHY(nf_state)) != ERR_OK) {
tms570_eth_debug_printf("tms570_eth_init_find_PHY: %d", retVal);
@@ -378,7 +382,7 @@ tms570_eth_init_hw(struct tms570_netif_state *nf_state)
* Start autonegotiation and check on completion later or
* when complete link register will be updated
*/
- PHY_auto_negotiate(nf_state->mdio_base, nf_state->phy_addr,
+ PHY_auto_negotiate(&nf_state->mdio.base, nf_state->phy_addr,
PHY_100BASETXDUPL_m | PHY_100BASETX_m |
PHY_10BASETDUPL_m | PHY_10BASET_m);
tms570_eth_debug_printf("autoneg started -- check on cable if it's
connected!\r\n");
@@ -442,19 +446,19 @@ tms570_eth_init_hw_post_init(struct tms570_netif_state
*nf_state)
/* wait for autonegotiation to be done or continue, when delay was reached */
uint32_t timeToWake = nf_state->waitTicksForPHYAneg + sys_jiffies();
- while (PHY_is_done_auto_negotiate(nf_state->mdio_base, nf_state->phy_addr)
== false &&
+ while (PHY_is_done_auto_negotiate(&nf_state->mdio.base, nf_state->phy_addr)
== false &&
timeToWake > sys_jiffies())
sys_arch_delay(20);
/* XXX: if init is not done at the startup,
* but couple days later, this might cause troubles */
- if (PHY_is_done_auto_negotiate(nf_state->mdio_base, nf_state->phy_addr) !=
false)
+ if (PHY_is_done_auto_negotiate(&nf_state->mdio.base, nf_state->phy_addr) !=
false)
tms570_eth_debug_printf("autoneg finished\n");
else
tms570_eth_debug_printf("autoneg timeout\n");
/* provide informations retrieved from autoneg to EMAC module */
- PHY_partner_ability_get(nf_state->mdio_base, nf_state->phy_addr,
®Content);
+ PHY_partner_ability_get(&nf_state->mdio.base, nf_state->phy_addr,
®Content);
if (regContent & (PHY_100BASETXDUPL_m | PHY_10BASETDUPL_m)) {
EMACDuplexSet(nf_state->emac_base, 1);
/* this is right place to implement transmit flow control if desired --
--
2.35.3
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