Hi Raymond, I think that allowing the hardware bits to be queried (and probably changed atomically while being read) would be useful.
Would such a feature be added in the future? I have a crazy hunch (but nowhere near the experience to prove it) that avoiding such "canary" style page faults could optimize things. As Kevin said: it’s an optimisation that was until recently only available on x86 processors. Because its an optimisation, it adds no functionality, only performance. We take performance very seriously. In fact, while seL4’s design is driven primarily by security, our philosophy is also that security is no excuse for bad performance. But, as Kevin also said, we’ve yet to see an important use case that will significantly benefit from this optimisation. There is no reason why we couldn’t support this optimisation, but, until someone convinces us that it’ll make a real difference, we have far more important work to do. A “would be nice” is not sufficient, I’m afraid. So, if you have an important and convincing use case that depends on this, then let us know. If you can come up with funding for the work, and we’re convinced it really helps, we’ll increase the priority. Soon (probably later today) I’ll post our development roadmap on [email protected]<mailto:[email protected]>. You’ll see that we’ve got plenty on our plate, all of which is important functionality that indisputably adds to seL4’s real-world usefulness, and therefore has priority. In fact, if we had more people, we would put them on accelerating the roadmap before we work on nice-to-haves. Gernot ________________________________ The information in this e-mail may be confidential and subject to legal professional privilege and/or copyright. National ICT Australia Limited accepts no liability for any damage caused by this email or its attachments.
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