On 9 Nov 2015, at 8:30 , Adrian Danis <[email protected]<mailto:[email protected]>> wrote:
I do not know the details of the arm926ej, but if its cache architecture is compatible then porting should be just a matter of converting the newer instructions to armv5 equivalents. If the cache is virtual addressed then some more thought and additional cache operations need to be placed through the kernel. the ARM926ej has virtually-addressed caches from memory, so you’ll have to flush in every context switch, or implement the complex fast-address-space switching logic we did on L4-embedded. Gernot ________________________________ The information in this e-mail may be confidential and subject to legal professional privilege and/or copyright. National ICT Australia Limited accepts no liability for any damage caused by this email or its attachments.
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