Nice! Just so I understand the setup: Does seL4 run in some super-privileged (hypervisor) mode or do seL4 and RTEMS run at the same privilege level on different cores? If it’s the latter, how is seL4 protected from the RTEMS side?
Gernot > On 16 Dec 2015, at 9:13 , Hesham Almatary <heshamelmat...@gmail.com> wrote: > > Hi all, > > I got an RTEMS port working for RISC-V architecture along with seL4. > This depends on my earlier seL4 port for RISC-V. > > RTEMS runs with support of seL4 microkernel, and it runs in Supervisor > mode (on another core). seL4 application would allocate and map memory > for it from its untyped memory (userspace), before off-loading it to > another core. > > seL4 application that loads/runs RTEMS is pretty much the same as SOS. > > For more details (and instructions) about how to build/run the project, see > the github repo of the port [1], and/or this blog post [2] > > [1] https://github.com/heshamelmatary/rtems-riscv > [2] > http://heshamelmatary.blogspot.co.uk/2015/12/rtems-port-for-risc-v-withwithout-sel4.html > > Cheers, > -- > Hesham > > _______________________________________________ > Devel mailing list > Devel@sel4.systems > https://sel4.systems/lists/listinfo/devel ________________________________ The information in this e-mail may be confidential and subject to legal professional privilege and/or copyright. National ICT Australia Limited accepts no liability for any damage caused by this email or its attachments. _______________________________________________ Devel mailing list Devel@sel4.systems https://sel4.systems/lists/listinfo/devel
