Are there any formal models of the ISA currently, or planned? I'd be
interested in working on one if so - currently mulling what it would take
to port seL4 to privileged-RISC, with the new availability of silicon that
implements some portion of its draft.

On Thu, Mar 8, 2018 at 7:29 AM, Matthew Wilson <diakop...@gmail.com> wrote:

> I'm also extremely happy to hear this.. Looking forward to reasonable (or
> at least effable) specs!
>
> On Wed, Mar 7, 2018 at 11:47 PM, Corey Richardson <co...@octayn.net>
> wrote:
>
>> I'm so happy to hear this!
>>
>> On Thu, Mar 8, 2018, at 00:18, gernot.hei...@data61.csiro.au wrote:
>> > Yes, RISC-V specs are high on my priorities. I’ll actually participate
>> > in some of the working groups.
>> >
>> > Gernot
>> >
>> > > On 8 Mar 2018, at 05:00, Kelly Dean <ke...@prtime.org> wrote:
>> > >
>> > > The RISC-V privileged ISA is not yet finalized. Have the seL4
>> developers reviewed the draft [1], in case they might have any
>> recommendations for improvement?
>> > >
>> > > For example, just last year a blunder (H-mode) was removed from the
>> draft per a proposal [2] on the mailing list.
>> > >
>> > > Finalization is planned for this year. Speak now or forever hold your
>> peace.
>> > >
>> > > The first public draft of the memory consistency model [3] was also
>> released just last December.
>> > >
>> > > And platform standardization, especially the IOMMU, is in progress.
>> > >
>> > > [1] https://content.riscv.org/wp-content/uploads/2017/05/riscv-p
>> rivileged-v1.10.pdf
>> > > [2] https://groups.google.com/a/groups.riscv.org/forum/#!msg/isa
>> -dev/SfEDPLU0NU4/WpAE_A4OBQAJ
>> > > [3] https://groups.google.com/a/groups.riscv.org/forum/#!topic/i
>> sa-dev/hKywNHBkAXM
>> > >
>> > > _______________________________________________
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>>
>> --
>> cmr
>> http://octayn.net/
>> +16038524272
>>
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>
>
>
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