On Mon, 2003-08-25 at 14:51, David Dawes wrote:
> >However on IA64 the concept of caching is overloaded, not only does it
> >refer to memory coherence but more importantly selects between two
> >vastly different memory spaces, RAM and IO. A cached access is
> >directed to RAM and a non-cached access is directed to IO (e.g. a pci
> >device).
>
> Does this mean that the video memory aperture on a PCI device is
> classified as RAM, or is there something else that ensures that
> cached accesses get directed to the PCI device in this case? Is
> the difference that this is a writeable region while the ROM is
> read-only?
I just received information from HP (thank you Bjorn Helgaas) that the
memory attribute does not direct access between RAM and IO, I was in
error. But what is critical is that the EFI MDT (Memory Descriptor
Table?) which is set up at boot time is the arbiter of which memory
attributes are used for various memory regions. User space mappings that
try to force cached vs. non-cached accesses are inappropriate, its not
their decision, rather it must be consistent with the EFI table which is
set up at boot time. There is a kernel patch that ignores the user
request for cached vs. uncached mappings and instead (indirectly)
consults the EFI MDT such that the memory attribute field in the TLB is
consistent with how that memory is referenced in the system, as
determined by the firmware (EFI). Beta RH kernel's were missing this
patch that had been present in earlier kernels. Bjorn tells me that with
the patch applied no changes need to be made to X for proper operation
and that the patch is in the upstream kernel sources.
FYI, the patch follows for those interested, note that O_SYNC is no
longer used as a trigger for non-cached access.
--- drivers/char/mem.c 2003-08-21 15:55:17.000000000 -0600
+++ /home/helgaas/linux/testing/drivers/char/mem.c 2003-08-13
10:54:25.000000000 -0600
@@ -180,6 +177,11 @@
test_bit(X86_FEATURE_CYRIX_ARR,
&boot_cpu_data.x86_capability) ||
test_bit(X86_FEATURE_CENTAUR_MCR,
&boot_cpu_data.x86_capability) )
&& addr >= __pa(high_memory);
+#elif defined(__ia64__)
+ struct page *page;
+
+ page = virt_to_page(__va(addr));
+ return !VALID_PAGE(page) || PageReserved(page);
#else
return addr >= __pa(high_memory);
#endif
@@ -194,7 +196,11 @@
* through a file pointer that was marked O_SYNC will be
* done non-cached.
*/
+#ifdef __ia64__
+ if (noncached_address(offset))
+#else
if (noncached_address(offset) || (file->f_flags & O_SYNC))
+#endif
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
/* Don't try to swap out physical pages.. */
--
John Dennis <[EMAIL PROTECTED]>
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