Michael Jastram schrieb: > Next, Writing is enabled by setting bits 0, 1, 4 and 5, as documented > in section 4.8.17 (page 70). In fact, this enables two, not just one > PAM register for R/W. But which ones?
> I don't understand where 0xcfe comes from! CONFIG_DATA starts at > 0xcfc (4.6.2., page 57); which of the 14 PAM Registers are we writing > to? Addressing these registers works as follows: The lower eight bits of the data written to 0xcf8 form the register, the lowest two bits are ignored (assumed 0), though. Then four consecutive registers appear at ports 0xcfc to 0xcff. For example: If you write 0x8000005a to 0xcf8 the registers 0x58 to 0x5b can be accessed. (Ignoring the two least significant bits of 0x5a gives 0x58.) So writing to 0xcfe affects register 0x5a which is responsible for the memory range from 0xc0000 to 0xcffff where the video BIOS resides. But I just received an email from Steve Tomljenovic: He already ported 855resolution to the i915. You can find his 915resolution at: http://www.geocities.com/stomljen/ Christian -- Christian Zietz - CHZ-Soft - [EMAIL PROTECTED] WWW: http://www.chzsoft.com.ar/ PGP-Key-ID: 0x6DA025CA _______________________________________________ Devel mailing list Devel@XFree86.Org http://XFree86.Org/mailman/listinfo/devel
