Following the discussion here: http://lists.ozlabs.org/pipermail/devicetree-discuss/2011-August/007301.html
The L2x0 L2 Cache Controllers support a combined interrupt line which can be used for several events (e.g. read/write/parity errors on tag/data RAM, event counter increment/overflow). Unfortunately the OF binding does not represent the interrupt. This patch adds an "interrupts" property to the L2x0 OF binding, representing the combined interrupt line. Signed-off-by: Mark Rutland <[email protected]> Cc: Rob Herring <[email protected]> Cc: Grant Likely <[email protected]> Cc: Arnd Bergmann <[email protected]> Cc: Olof Johansson <[email protected]> Cc: Barry Song <[email protected]> Cc: Will Deacon <[email protected]> --- Documentation/devicetree/bindings/arm/l2cc.txt | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt index f50e021..7ca5216 100644 --- a/Documentation/devicetree/bindings/arm/l2cc.txt +++ b/Documentation/devicetree/bindings/arm/l2cc.txt @@ -28,6 +28,7 @@ Optional properties: - arm,filter-ranges : <start length> Starting address and length of window to filter. Addresses in the filter window are directed to the M1 port. Other addresses will go to the M0 port. +- interrupts : 1 combined interrupt. Example: @@ -39,4 +40,5 @@ L2: cache-controller { arm,filter-latency = <0x80000000 0x8000000>; cache-unified; cache-level = <2>; + interrupts = <45>; }; -- 1.7.0.4 _______________________________________________ devicetree-discuss mailing list [email protected] https://lists.ozlabs.org/listinfo/devicetree-discuss
