> -----Original Message-----
> From: Mitch Bradley [mailto:[email protected]]
>
> I would be tempted to add another level of hierarchy as a container for
> the two FPEs on CS2.
>
Hi, Mitch.
As a long time Forth(er), I'm somewhat honoured to have this exchange with you
8-)
Do you mean something like this????
localbus@ffe124000 {
compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
reg = <0xf 0xfe124000 0 0x1000>;
interrupts = <25 2 0 0>;
interrupt-parent = <&mpic>;
#address-cells = <2>;
#size-cells = <1>;
/* Local bus region mappings */
ranges = <0 0 0xf 0xe8000000 0x08000000 /* CS0: Boot
flash */
1 0 0xf 0xd0000000 0x7fff /* CS1: FPGA0 -
LIM */
2 0 0xf 0xd1000000 0x7fff /* CS2: FPGA1 -
FPE1 */
2 1 0xf 0xd2000000 0x7fff >; /* CS2: FPGA2 -
FPE2 */
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x08000000>;
bank-width = <2>;
device-width = <2>;
#size-cells = <1>;
#address-cells = <1>;
partition@0 {
label = "rcw";
reg = <0x0 0x20000>;
read-only;
};
partition@40000 {
label = "saveenv";
reg = <0x40000 0x20000>;
};
partition@7000000 {
label = "fman-firmware";
reg = <0x7000000 0x20000>;
read-only;
};
partition@7f80000 {
label = "u-boot";
reg = <0x7f80000 0x80000>;
read-only;
};
};
lim: fpga@1, {
}
nitro: daughtercard@2 {
fpe1: fpga@2,0 {
}
fpe2: fpga@2,1 {
}
}
}
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