On 15/03/12 02:56, Thierry Reding wrote: > Signed-off-by: Thierry Reding <[email protected]> > --- > Changes in v3: > - update PWM ops for changes in patch 2
Couple of quick notes, mostly for future work. > + /* NOTE: the clock to PWM has to be enabled first > + * before writing to the registers > + */ > + clk_enable(pc->clk); Should be fixed to also call clk_prepare (and clk_unprepare after clk_disable). Could be done in a follow up patch. > + __raw_writel(prescale, pc->mmio_base + offset + PWMCR); > + __raw_writel(dc, pc->mmio_base + offset + PWMDCR); > + __raw_writel(pv, pc->mmio_base + offset + PWMPCR); Should we fix this driver to use readl/writel instead of the __raw variants? The memory is properly ioremaped, and to my understanding the __raw memory accessors should be avoided outside of core code. This could be done in a follow up patch if you want to keep this patch as mostly just a move of the code. ~Ryan _______________________________________________ devicetree-discuss mailing list [email protected] https://lists.ozlabs.org/listinfo/devicetree-discuss
