With the migration of Exynos4 clocks to use common clock framework, the old styled 'xtal' clock is not used anymore. Instead, the clock 'fin_pll' is used as the tick clock for mct controller.
Cc: Kukjin Kim <[email protected]> Signed-off-by: Thomas Abraham <[email protected]> --- arch/arm/mach-exynos/mct.c | 8 +++++--- 1 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c index cd061b2..47bc6b35 100644 --- a/arch/arm/mach-exynos/mct.c +++ b/arch/arm/mach-exynos/mct.c @@ -489,10 +489,12 @@ static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = { static void __init exynos4_timer_resources(struct device_node *np) { - struct clk *mct_clk; - mct_clk = clk_get(NULL, "xtal"); + struct clk *tick_clk; - clk_rate = clk_get_rate(mct_clk); + tick_clk = clk_get(NULL, "fin_pll"); + if (IS_ERR(tick_clk)) + panic("%s: unable to determine tick clock rate\n", __func__); + clk_rate = clk_get_rate(tick_clk); reg_base = (np) ? of_iomap(np, 0) : S5P_VA_SYSTIMER; if (!reg_base) -- 1.7.4.4 _______________________________________________ devicetree-discuss mailing list [email protected] https://lists.ozlabs.org/listinfo/devicetree-discuss
