On Friday 28 December 2012 11:26 PM, Andrew Lunn wrote:
Is this single CPU or multi-cpu machine ?
Its a uniprocessor.
That should work then.
Even though the cpu_do_idle()
has just couple of instructions, there can be lot more happening in
background especially with multi masters system. It might be safe if the
single CPU is the only master accessing DDR. In multi-master, multi-CPU
scenario though it can't work reliably.
There are DMA engines which could be active, moving stuff into/out of
memory.
Sure but you must be stopping DMA before entering idle where DDR can
enter into self-refresh otherwise DMA transfer will be aborted. DDR
controller also can take care of such a scenario by not entering into
self refresh when DMA is active and self refresh command is issued.
Having said that, this code is not new, it is just getting a new home.
There has not been problems before. Having this 256 cycle delay etc,
suggests the hardware design is robust.
Thanks for information that it is robust and working well. I was just
curious having faced some issues on this topic in past.
Regards
Santosh
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