On 01/08/2013 03:57 AM, Laxman Dewangan wrote: > NVIDIA's Tegra has multiple UART controller which supports: > - APB DMA based controller fifo read/write. > - End Of Data interrupt in incoming data to know whether end > of frame achieve or not. > - HW controlled RTS and CTS flow control to reduce SW overhead. > > Add serial driver to use all above feature. > > Signed-off-by: Laxman Dewangan <[email protected]> > Acked-by: Alan Cox <[email protected]>
The DT binding part of this patch, Reviewed-by: Stephen Warren <[email protected]> _______________________________________________ devicetree-discuss mailing list [email protected] https://lists.ozlabs.org/listinfo/devicetree-discuss
