On 01/12/2013 09:10 PM, Stephen Warren wrote: > On 01/12/2013 08:54 AM, Rob Herring wrote: >> On 01/10/2013 07:47 AM, Michal Simek wrote: >>> Hi Rob, Mark, Grant and others, >>> >>> I want to check with you the location of ARM pmu node >>> I see that >>> 1) highbank and dbx5x0 have it in soc node >>> >>> 2) vexpress and tegra have no main bus and pmu is in root like all >>> others devices. >>> (Any reason no to have main bus? Does it mean that there is no bus or >>> that all >>> devices are accessible?) >> >> That seems really wrong in general. Any memory mapped device is on a bus >> of some kind. I'm not sure the reasoning. Perhaps Stephen can explain. > > I saw no need to have add a bus node (there wasn't one before I started > touching DT on Tegra); the top-level of the DT represents the CPU's > entire view of the address space and has #address-cells/#size-cells, so > devices get probed there just fine, whether they're addressed MMIO > devices or not.
The top level doesn't really represent a bus. It is basically all the things that have no hierarchical relationship (cpu, memory, chosen, peripheral buses). The reason to have a bus node is to define "simple-bus" While I would do it differently, I don't recommend changing it at this point. Although, this could be changed without compatibility issues. Rob _______________________________________________ devicetree-discuss mailing list [email protected] https://lists.ozlabs.org/listinfo/devicetree-discuss
