On 01/22/2013 02:46 PM, Lucas Stach wrote: > No Tegra Platform is running PLL_P at another rate than 216MHz, nor is > any using an other PLL as UART source clock. Move attribute into SoC > level dtsi file to slim down board DT files.
I've applied the series to Tegra's for-3.9/dt branch. _______________________________________________ devicetree-discuss mailing list [email protected] https://lists.ozlabs.org/listinfo/devicetree-discuss
