On Fri, Nov 1, 2013 at 5:13 AM, Ian Campbell <[email protected]> wrote: > GICv2 (Cortex A15/GIC 400) have CPU interface registers up to offset 0x1004 > (the 32-bit GICC_DIR register a 0x1000). The GIC 400 documentation specifies > the CPU interface region as being 0x2000 in size. > > Update all DTS entries claiming "arm,cortex-a15-gic" compatibility. Of these I > only have personal experience with the vexpress a Calxeda (ecx) platforms and > annecdotal evidence for omap and exynos. For the others I'm just assuming. > > Also update the example a15 binding in the documentation. > > The "Texas Instruments Keystone 2 SoC" platform which claim to have an a15 > compatible GIC but does not include the GICH/GICV registers. I've not touched > that here. > > Signed-off-by: Ian Campbell <[email protected]> > Cc: [email protected] > Cc: [email protected]
Acked-by: Rob Herring <[email protected]> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
