From: Stephen Warren <[email protected]> Tegra124 has 4 MMC controllers just like previous versions of the SoC. Note that there are some non-backwards-compatible HW differences, and hence a new DT compatible value must be used to describe the HW.
Also enable the relevant controllers in the Venice2 board DT. Signed-off-by: Stephen Warren <[email protected]> --- arch/arm/boot/dts/tegra124-venice2.dts | 11 ++++++++++ arch/arm/boot/dts/tegra124.dtsi | 40 ++++++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index a0b028384658..bc502112eb04 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -25,6 +25,17 @@ nvidia,sys-clock-req-active-high; }; + sdhci@700b0400 { + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + status = "okay"; + bus-width = <4>; + }; + + sdhci@700b0600 { + status = "okay"; + bus-width = <8>; + }; + clocks { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 96e051e13f76..200373236aaa 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -190,6 +190,46 @@ clock-names = "pclk", "clk32k_in"; }; + sdhci@700b0000 { + compatible = "nvidia,tegra124-sdhci"; + reg = <0x700b0000 0x200>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; + resets = <&tegra_car 14>; + reset-names = "sdhci"; + status = "disable"; + }; + + sdhci@700b0200 { + compatible = "nvidia,tegra124-sdhci"; + reg = <0x700b0200 0x200>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; + resets = <&tegra_car 9>; + reset-names = "sdhci"; + status = "disable"; + }; + + sdhci@700b0400 { + compatible = "nvidia,tegra124-sdhci"; + reg = <0x700b0400 0x200>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; + resets = <&tegra_car 69>; + reset-names = "sdhci"; + status = "disable"; + }; + + sdhci@700b0600 { + compatible = "nvidia,tegra124-sdhci"; + reg = <0x700b0600 0x200>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; + resets = <&tegra_car 15>; + reset-names = "sdhci"; + status = "disable"; + }; + cpus { #address-cells = <1>; #size-cells = <0>; -- 1.8.1.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
