On Fri, Dec 13, 2013 at 12:39 PM, Felipe Balbi <[email protected]> wrote: > On Fri, Dec 13, 2013 at 09:23:45AM +0800, Peter Chen wrote: >> After clear portsc.phcd, PHY needs 200us stable time for switch >> 32K clock to AHB clock. >> >> Signed-off-by: Peter Chen <[email protected]> >> --- >> drivers/usb/phy/phy-mxs-usb.c | 11 +++++++++++ >> 1 files changed, 11 insertions(+), 0 deletions(-) >> >> diff --git a/drivers/usb/phy/phy-mxs-usb.c b/drivers/usb/phy/phy-mxs-usb.c >> index 885f8d9..68bd981 100644 >> --- a/drivers/usb/phy/phy-mxs-usb.c >> +++ b/drivers/usb/phy/phy-mxs-usb.c >> @@ -156,6 +156,15 @@ static inline bool is_imx6sl_phy(struct mxs_phy >> *mxs_phy) >> return mxs_phy->data == &imx6sl_phy_data; >> } >> >> +/* >> + * PHY needs some 32K cycles to switch from 32K clock to >> + * bus (such as AHB/AXI, etc) clock. >> + */ >> +static void mxs_phy_clock_switch_delay(void) >> +{ >> + usleep_range(300, 400); >> +} > > shouldn't this be handled by clk_set_parent() itself ? > > --
This clock switching is finished by hardware, no related clkgates are at clock module. -- BR, Peter Chen -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
