On Tue, Jan 21, 2014 at 11:49:01AM +0000, Dave Martin wrote: > I do have a worry that because the kernel won't normally use this > information, by default it will get pasted between .dts files, won't get > tested and will be wrong rather often. It also violates the DT principle > that probeable information should not be present in the DT -- ePAPR > obviously envisages systems where cache geometry information is not > probeable, but that's not the case for architected caches on ARM, except > in rare cases where the CLIDR is wrong.
That statement is wrong. There are caches on ARM CPUs where there is no CLIDR register. I suggest reading the earlier DDI0100 revisions. -- FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up. Estimation in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad. Estimate before purchase was "up to 13.2Mbit". -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
