On Mon, Jan 27, 2014 at 01:03:09PM +0100, Markus Pargmann wrote:

>       case SND_SOC_BIAS_STANDBY:
> +             /* Switch off master clock */
> +             if (!IS_ERR(aic32x4->mclk))
> +                     clk_disable_unprepare(aic32x4->mclk);
> +
>               /* Switch off PLL */
>               snd_soc_update_bits(codec, AIC32X4_PLLPR,
>                                   AIC32X4_PLLEN, 0);

This looks like it's disabling the MCLK before disabling the PLL - if
the two are being disabled together I would expect to see the other way
around.

Otherwise this looks good to me.

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