From: Keerthy <[email protected]>

Change the parent of apll_pcie_in_clk_mux to dpll_pcie_ref_m2ldo_ck
from dpll_pcie_ref_ck.

Signed-off-by: Keerthy <[email protected]>
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
---
 arch/arm/boot/dts/dra7xx-clocks.dtsi |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi 
b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index d909484..9e0bb09 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1152,7 +1152,7 @@
 
        apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
                compatible = "ti,mux-clock";
-               clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
+               clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
                #clock-cells = <0>;
                reg = <0x021c 0x4>;
                ti,bit-shift = <7>;
-- 
1.7.9.5

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