Add irq muxing and irq-mapping dt bindings documentation.
Signed-off-by: Boris BREZILLON <[email protected]>
---
.../bindings/interrupt-controller/atmel,aic.txt | 42 +++++++++++++++++++-
1 file changed, 41 insertions(+), 1 deletion(-)
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt
b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt
index 2742e9c..d46ec8e 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.txt
@@ -18,8 +18,33 @@ Required properties:
The third cell is used to specify the irq priority from 0 (lowest) to 7
(highest).
- reg: Should contain AIC registers location and length
+- #address-cells: Shall be 2. The first cell encodes the irq line (or irq id).
+ The second cell encodes the register offset within the iomem range.
+- #size-cells: Shall be 1.
+- ranges: Defines the iomem ranges attached to a given irq line (e.i. irq
+ line 1 <=> SYSC range).
- atmel,external-irqs: u32 array of external irqs.
+Optional properties:
+- atmel,irq-mapping: u32 mask array representing the available irqs:
+ e.i. : atmel,irq-mapping = <0xffff1fff> => irqs 13 to 15 are unavailables
+
+Optional children nodes:
+- muxed irq entries:
+ Required properties:
+ * compatible: Shall be
+ "atmel,aic-mux-1reg-irq": irq enable/disable/retrieve-status is done by
+ setting/clearing/reading flags in a specific register
+ or
+ "atmel,aic-mux-3reg-irq": irq enable/disable/retrieve-status is done
+ by writing/reading flags in specific enable/disable/mask registers
+ * reg: encode the interrupt control register.
+ The first cell encode the irq line.
+ The second cell encode the offset register within its iomem range
+ The last cell encode the iomem region size (should always be set to 0x4).
+ * atmel,aic-mux-reg-mask: define the mask used to disable the interrupts
+ generated by the muxed entry.
+
Examples:
/*
* AIC
@@ -29,11 +54,26 @@ Examples:
interrupt-controller;
interrupt-parent;
#interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <1>;
reg = <0xfffff000 0x200>;
+ ranges = <0x1 0x0 0xffffc000 0x4000>;
+
+ dbgu_irq: irq@1,320c {
+ compatible = "atmel,aic-mux-3reg-irq";
+ reg = <1 0x320c 0x4>;
+ atmel,aic-mux-reg-mask = <0xc0001afb>;
+ };
+
+ pmc_irq: irq@1,3c64 {
+ compatible = "atmel,aic-mux-3reg-irq";
+ reg = <1 0x3c64 0x4>;
+ atmel,aic-mux-reg-mask = <0xf0f>;
+ };
};
/*
- * An interrupt generating device that is wired to an AIC.
+ * A device generating interrupts wired to the AIC.
*/
dma: dma-controller@ffffec00 {
compatible = "atmel,at91sam9g45-dma";
--
1.7.9.5
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