Add APB0 gates support for the A31 SoC. This gates are controlled by the PRCM (Power/Reset/Clock Management) block and thus will act on a different iomem range.
Signed-off-by: Boris BREZILLON <[email protected]> --- drivers/clk/sunxi/clk-sunxi.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index abb6c5a..f9b11c3 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -718,6 +718,10 @@ static const struct gates_data sun5i_a13_apb0_gates_data __initconst = { .mask = {0x61}, }; +static const struct gates_data sun6i_a31_apb0_gates_data __initconst = { + .mask = { 0x7f }, +}; + static const struct gates_data sun7i_a20_apb0_gates_data __initconst = { .mask = { 0x4ff }, }; @@ -1013,6 +1017,7 @@ static const struct of_device_id clk_gates_match[] __initconst = { {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &sun4i_apb0_gates_data,}, {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,}, {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,}, + {.compatible = "allwinner,sun6i-a31-apb0-gates-clk", .data = &sun6i_a31_apb0_gates_data,}, {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,}, {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &sun4i_apb1_gates_data,}, {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,}, -- 1.8.3.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
