To support MIPI DSI command mode interface, the display controller requires the CPU mode timings which is the panel specific data.
Signed-off-by: YoungJun Cho <[email protected]> Acked-by: Inki Dae <[email protected]> Acked-by: Kyungmin Park <[email protected]> --- include/drm/drm_panel.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h index c2ab77a..67e6871 100644 --- a/include/drm/drm_panel.h +++ b/include/drm/drm_panel.h @@ -46,6 +46,24 @@ struct drm_panel { struct list_head list; }; +/** + * struct drm_panel_cpu_mode_timings - describe cpu mode timing settings + * @cs_setup: clock cycles for the active period of address signal is enabled + * until chip select is enabled in CPU mode interface + * @wr_setup: clock cycles for the active period of CS signal is enabled until + * write signal is enabled in CPU mode interface + * @wr_actve: clock cycles for the active period of CS is enabled in CPU mode + * interface + * @wr_hold: clock cycles for the active period of CS is disabled until write + * signal is disabled in CPU mode interface + */ +struct drm_panel_cpu_mode_timings { + unsigned int cs_setup; + unsigned int wr_setup; + unsigned int wr_active; + unsigned int wr_hold; +}; + static inline int drm_panel_disable(struct drm_panel *panel) { if (panel && panel->funcs && panel->funcs->disable) -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
