Hi Rahul, On 16.05.2014 12:39, Rahul Sharma wrote: > [snip] >> + gate->lock = &clkout_lock; >> + >> + mux->reg = reg + EXYNOS_PMU_DEBUG_REG; >> + mux->mask = EXYNOS_CLKOUT_MUX_MASK; >> + mux->shift = EXYNOS_CLKOUT_MUX_SHIFT; >> + mux->lock = &clkout_lock; >> + >> + clk = clk_register_composite(NULL, "clkout", parent_names, >> + parent_count, &mux->hw, >> + &clk_mux_ops, NULL, NULL, &gate->hw, >> + &clk_gate_ops, 0); >> + if (IS_ERR(clk)) >> + goto err_unmap; >> + > > Hi Tomasz, > > Do we really need a composite clock here? How about registering > a mux and a gate separately?
What's wrong with a composite clock? It simplifies the code as just a single clock needs to be registered. I don't see any drawbacks compared to registering two clocks separately. Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
