Hi, On 26.05.2014 13:56, Shaik Ameer Basha wrote: > From: Prathyush K <[email protected]> > > While powering on/off a local powerdomain in exynos5 chipsets, the input > clocks to each device gets modified. This behaviour is based on the > SYSCLK_SYS_PWR_REG registers. > E.g. SYSCLK_MFC_SYS_PWR_REG = 0x0, the parent of input clock to MFC > (aclk333) gets modified to oscclk > = 0x1, no change in clocks. > The recommended value of SYSCLK_SYS_PWR_REG before power gating any > domain is 0x0. So we must also restore the clocks while powering on a > domain everytime. > > This patch adds the framework for getting the required mux and parent clocks > through a power domain device node. With this patch, while powering off > a domain, parent is set to oscclk and while powering back on, its re-set > to the correct parent which is as per the recommended pd on/off > sequence. > > Signed-off-by: Prathyush K <[email protected]> > Signed-off-by: Andrew Bresticker <[email protected]> > Signed-off-by: Arun Kumar K <[email protected]> > Signed-off-by: Shaik Ameer Basha <[email protected]> > --- > .../bindings/arm/exynos/power_domain.txt | 20 +++++++ > arch/arm/mach-exynos/pm_domains.c | 59 > +++++++++++++++++++- > 2 files changed, 78 insertions(+), 1 deletion(-) >
Reviewed-by: Tomasz Figa <[email protected]> -- Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
