The clock block of Exynos3250 add new properties to support cpu clock provider. To register cpu clock provider of Exynos3250, must need armclk-provider-table which includes various dividers to change CPU clock to support Exynos3250 cpufreq.
Cc: Thomas Abraham <[email protected]> Cc: Tomasz Figa <[email protected]> Cc: Rob Herring <[email protected]> Cc: Pawel Moll <[email protected]> Cc: Mark Rutland <[email protected]> Cc: Ian Campbell <[email protected]> Cc: Kumar Gala <[email protected]> Cc: <[email protected]> Signed-off-by: Chanwoo Choi <[email protected]> Acked-by: Kyungmin Park <[email protected]> --- .../devicetree/bindings/clock/exynos3250-clock.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/exynos3250-clock.txt b/Documentation/devicetree/bindings/clock/exynos3250-clock.txt index aadc9c5..189b506 100644 --- a/Documentation/devicetree/bindings/clock/exynos3250-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos3250-clock.txt @@ -13,6 +13,25 @@ Required Properties: - #clock-cells: should be 1. +- samsung,armclk-divider-table: when the frequency of the APLL is changed + the divider clocks in CMU_CPU clock domain also need to be updated. These + divider clocks have SoC specific divider clock output requirements for a + specific APLL clock speeds. When APLL clock rate is changed, these divider + clocks are reprogrammed with pre-determined values in order to maintain the + SoC specific divider clock outputs. This property lists the divider values + for divider clocks in the CMU_CPU block for supported APLL clock speeds. + The format of each entry included in the arm-frequency-table should be + as defined below + + cell #1: expected arm clock parent frequency + cell #2 ~ cell #7: value of clock divider in the following order + corem_ratio, atb_ratio, pclk_dbg_ratio, apll_ratio, + copy_ratio, hpm_ratio + +- samsung,armclk-cells: defines the number of cells in + samsung,armclk-divider-table property. The value of this property depends on + the SoC type. + Each clock is assigned an identifier and client nodes can use this identifier to specify the clock which they consume. @@ -26,6 +45,19 @@ Example 1: An example of a clock controller node is listed below. compatible = "samsung,exynos3250-cmu"; reg = <0x10030000 0x20000>; #clock-cells = <1>; + + samsung,armclk-cells = <7>; + samsung,armclk-divider-table = + <1000000 1 4 7 1 7 7>, + <900000 1 3 7 1 7 7>, + <800000 1 3 7 1 7 7>, + <700000 1 3 7 1 7 7>, + <600000 1 3 7 1 7 7>, + <500000 1 3 7 1 7 7>, + <400000 1 3 7 1 7 7>, + <300000 1 3 5 1 7 7>, + <200000 1 3 3 1 7 7>, + <100000 1 1 1 1 7 7>; }; Example 2: UART controller node that consumes the clock generated by the clock -- 1.8.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
