On 06/30/2014 05:45 PM, Murali Karicheri wrote:
Add API dw_pcie_v3_65_host_init() to support host controller initialization for Keystone PCI driver. The Keystone PCI uses v3.65 version of the DW hardware identified by compatibility string "dw,snps-pcie-v3.65". This allow for different treatment for this version of the h/w during host initialization. Key differences in v3.65 DW h/w are 1. No ATU support 2. Legacy and MSI irq functions are implemented in application register space 3. MSI interrupts are multiplexed over 8 IRQ lines to the Host side. So a msi irq chip is needed and the irq domain ops ptr is passed in dw_pcie_v3_65_host_init() to allow re-use of common MSI code in dw core. The Keystone PCI host controller requires a modified pci scan function to allow setup BAR0 for EP's access to MSI_IRQ register in application register to raise MSI irq. So a ptr to pci hw ops struct is passed to the host init code.Keystone PCI controller re-uses the DW Core driver code wherever there is common functionality. So this patch makes these functions global and added their prototypes in pcie-designware.h to allow re-use on Keystone. Signed-off-by: Murali Karicheri<[email protected]> CC: Santosh Shilimkar<[email protected]> CC: Russell King<[email protected]> CC: Grant Likely<[email protected]> CC: Rob Herring<[email protected]> CC: Mohit Kumar<[email protected]> CC: Jingoo Han<[email protected]> CC: Bjorn Helgaas<[email protected]> CC: Pratyush Anand<[email protected]> CC: Richard Zhu<[email protected]> CC: Kishon Vijay Abraham I<[email protected]> CC: Marek Vasut<[email protected]> CC: Arnd Bergmann<[email protected]> CC: Pawel Moll<[email protected]> CC: Mark Rutland<[email protected]> CC: Ian Campbell<[email protected]> CC: Kumar Gala<[email protected]> CC: Randy Dunlap<[email protected]> CC: Grant Likely<[email protected]> --- .../devicetree/bindings/pci/designware-pcie.txt | 2 + drivers/pci/host/pcie-designware.c | 39 ++++++++++++++++++-- drivers/pci/host/pcie-designware.h | 7 ++++ 3 files changed, 44 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt index d0d15ee..0cb10c0 100644 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt @@ -2,6 +2,8 @@ Required properties: - compatible: should contain "snps,dw-pcie" to identify the core. + Additionally contains "dw,snps-pcie-v3.65" to identify v3.65 version of the DW + hardware. - #address-cells: set to<3> - #size-cells: set to<2> - device_type: set to "pci" diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index c11e4de..4dcbebe 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -556,6 +556,37 @@ static int dw_pcie_msi_host_init(struct pcie_port *pp, return 0; } +int __init dw_pcie_v3_65_host_init(struct pcie_port *pp, struct hw_pci *hw, + struct device_node *msi_irqc_np, + const struct irq_domain_ops *msi_irq_ops) +{ + int ret = -EINVAL; + + /* check if compatible with v3.65 DW h/w */ + if (!of_device_is_compatible(pp->dev->of_node, "dw,snps-pcie-v3.65")) { + dev_err(pp->dev, + "PCI Controller not compatible with v3.65 DW h/w\n"); + goto out; + } + pp->version = DW_HW_V3_65; + + /* v3.65 PCI controller is expected to provide its own PCI h/w ops */ + if (!hw || !msi_irq_ops) { + dev_err(pp->dev, + "v3.65 PCI Controllers doesn't provide %s\n", + (hw == NULL) ? "PCI hw ops" : "PCI MSI irq domain ops"); + goto out; + } + + ret = dw_pcie_msi_host_init(pp, msi_irqc_np, msi_irq_ops); + if (ret) + goto out; + + ret = dw_pcie_common_host_init(pp, hw); +out: + return ret; +} + int __init dw_pcie_host_init(struct pcie_port *pp) { int ret; @@ -763,7 +794,7 @@ static struct pci_ops dw_pcie_ops = { .write = dw_pcie_wr_conf, }; -static int dw_pcie_setup(int nr, struct pci_sys_data *sys) +int dw_pcie_setup(int nr, struct pci_sys_data *sys) { struct pcie_port *pp; @@ -786,7 +817,7 @@ static int dw_pcie_setup(int nr, struct pci_sys_data *sys) return 1; } -static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) +struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) { struct pci_bus *bus; struct pcie_port *pp = sys_to_pcie(sys); @@ -803,7 +834,7 @@ static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys) return bus; } -static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata); int irq; @@ -815,7 +846,7 @@ static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return irq; } -static void dw_pcie_add_bus(struct pci_bus *bus) +void dw_pcie_add_bus(struct pci_bus *bus) { if (IS_ENABLED(CONFIG_PCI_MSI)) { struct pcie_port *pp = sys_to_pcie(bus->sysdata); diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index db0260f..2681826 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -81,4 +81,11 @@ void dw_pcie_msi_init(struct pcie_port *pp); int dw_pcie_link_up(struct pcie_port *pp); void dw_pcie_setup_rc(struct pcie_port *pp); int dw_pcie_host_init(struct pcie_port *pp); +int dw_pcie_v3_65_host_init(struct pcie_port *pp, struct hw_pci *hw, + struct device_node *msi_irqc_np, + const struct irq_domain_ops *msi_irq_ops); +int dw_pcie_setup(int nr, struct pci_sys_data *sys); +struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys); +void dw_pcie_add_bus(struct pci_bus *bus); +int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); #endif /* _PCIE_DESIGNWARE_H */
DT Maintainers, Could you provide your comments or Ack for the DT update made in this patch? Thanks Murali -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
