On Mon, 14 Jul 2014, Kishon Vijay Abraham I wrote: > On Wednesday 09 July 2014 04:32 PM, Rajendra Nayak wrote: > > On Wednesday 09 July 2014 02:32 PM, Kishon Vijay Abraham I wrote: > >> Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC. > >> > >> Cc: Tony Lindgren <[email protected]> > >> Cc: Russell King <[email protected]> > >> Cc: Paul Walmsley <[email protected]> > >> Signed-off-by: Kishon Vijay Abraham I <[email protected]> > >> Tested-by: Kishon Vijay Abraham I <[email protected]> > >> --- > >> Changes from v1: > >> * changed the clock domain to "pcie_clkdm" > >> * Added PCIe as a slave port for l3_main. > > > > Looks good to me, > > Reviewed-by: Rajendra Nayak <[email protected]> > > Paul, > > Can you pick this one?
Yep, queued for 3.17. - Paul -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
