Signed-off-by: Xiubo Li <[email protected]>
Cc: Varka Bhadram <[email protected]>
---
.../devicetree/bindings/sound/fsl,spdif.txt | 82 +++++++++++-----------
1 file changed, 41 insertions(+), 41 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.txt
b/Documentation/devicetree/bindings/sound/fsl,spdif.txt
index 3e9e82c8..d37bfc2 100644
--- a/Documentation/devicetree/bindings/sound/fsl,spdif.txt
+++ b/Documentation/devicetree/bindings/sound/fsl,spdif.txt
@@ -6,54 +6,54 @@ a fibre cable.
Required properties:
- - compatible : Compatible list, must contain "fsl,imx35-spdif".
+- compatible: Compatible list, must contain "fsl,imx35-spdif".
- - reg : Offset and length of the register set for the device.
+- reg: Offset and length of the register set for the device.
- - interrupts : Contains the spdif interrupt.
+- interrupts: Contains the spdif interrupt.
- - dmas : Generic dma devicetree binding as described in
- Documentation/devicetree/bindings/dma/dma.txt.
+- dmas: Generic dma devicetree binding as described in
+ Documentation/devicetree/bindings/dma/dma.txt.
- - dma-names : Two dmas have to be defined, "tx" and "rx".
+- dma-names: Two dmas have to be defined, "tx" and "rx".
- - clocks : Contains an entry for each entry in clock-names.
+- clocks: Contains an entry for each entry in clock-names.
- - clock-names : Includes the following entries:
- "core" The core clock of spdif controller
- "rxtx<0-7>" Clock source list for tx and rx clock.
- This clock list should be identical to
- the source list connecting to the spdif
- clock mux in "SPDIF Transceiver Clock
- Diagram" of SoC reference manual. It
- can also be referred to TxClk_Source
- bit of register SPDIF_STC.
+- clock-names: Includes the following entries:
+ "core" -- The core clock of spdif controller
+ "rxtx<0-7>" -- Clock source list for tx and rx clock.
+ This clock list should be identical to
+ the source list connecting to the spdif
+ clock mux in "SPDIF Transceiver Clock
+ Diagram" of SoC reference manual. It
+ can also be referred to TxClk_Source
+ bit of register SPDIF_STC.
- - big-endian : If this property is absent, the native endian mode will
- be in use as default, or the big endian mode will be in use for all the
- device registers.
+- big-endian: If this property is absent, the native endian mode will
+ be in use as default, or the big endian mode will be in
+ use for all the device registers.
Example:
-spdif: spdif@02004000 {
- compatible = "fsl,imx35-spdif";
- reg = <0x02004000 0x4000>;
- interrupts = <0 52 0x04>;
- dmas = <&sdma 14 18 0>,
- <&sdma 15 18 0>;
- dma-names = "rx", "tx";
-
- clocks = <&clks 197>, <&clks 3>,
- <&clks 197>, <&clks 107>,
- <&clks 0>, <&clks 118>,
- <&clks 62>, <&clks 139>,
- <&clks 0>;
- clock-names = "core", "rxtx0",
- "rxtx1", "rxtx2",
- "rxtx3", "rxtx4",
- "rxtx5", "rxtx6",
- "rxtx7";
-
- big-endian;
- status = "okay";
-};
+ spdif: spdif@02004000 {
+ compatible = "fsl,imx35-spdif";
+ reg = <0x02004000 0x4000>;
+ interrupts = <0 52 0x04>;
+ dmas = <&sdma 14 18 0>,
+ <&sdma 15 18 0>;
+ dma-names = "rx", "tx";
+
+ clocks = <&clks 197>, <&clks 3>,
+ <&clks 197>, <&clks 107>,
+ <&clks 0>, <&clks 118>,
+ <&clks 62>, <&clks 139>,
+ <&clks 0>;
+ clock-names = "core", "rxtx0",
+ "rxtx1", "rxtx2",
+ "rxtx3", "rxtx4",
+ "rxtx5", "rxtx6",
+ "rxtx7";
+
+ big-endian;
+ status = "okay";
+ };
--
1.8.5
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