From: Frank Li
> From: Fugang Duan <[email protected]>
>
> Since enet-avb has 64 bytes alignment limitation for rx DMA transfer.
> The previous enet IP for ARM platform has 16 bytes alignment for tx
> DMA transfer.
Do you mean rx or tx here? or both??
And can we beat up the hardware designers to stop these restrictions
on rx (in particular) ethernet buffer alignments?
A device isn't suitable for ethernet unless is can write the destination
mac address to a 4n+2 boundary.
David
> 64 is the an integral number of 16, so change alignment
> to 64 bytes for all ARM platform, which don't impact the performance
> of previous platform.
>
> Signed-off-by: Fugang Duan <[email protected]>
> Signed-off-by: Frank Li <[email protected]>
> ---
> drivers/net/ethernet/freescale/fec_main.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/freescale/fec_main.c
> b/drivers/net/ethernet/freescale/fec_main.c
> index a232245..b388e29f 100644
> --- a/drivers/net/ethernet/freescale/fec_main.c
> +++ b/drivers/net/ethernet/freescale/fec_main.c
> @@ -65,7 +65,7 @@
> static void set_multicast_list(struct net_device *ndev);
>
> #if defined(CONFIG_ARM)
> -#define FEC_ALIGNMENT 0xf
> +#define FEC_ALIGNMENT 0x3f
> #else
> #define FEC_ALIGNMENT 0x3
> #endif
> --
> 1.9.1
>
> --
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