Hello.
On 10/07/2014 04:19 PM, Yoshihiro Shimoda wrote:
Since this board doesn't have USB ID pin, we assumes the GP5_18 (USB0_PWEN)
is an ID pin because the gpio is high when the SW5 is Pin 3 side.
Signed-off-by: Yoshihiro Shimoda <[email protected]>
---
arch/arm/boot/dts/r8a7790-lager.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts
b/arch/arm/boot/dts/r8a7790-lager.dts
index 719979e..011254a 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -446,3 +446,8 @@
};
};
};
+
+&hsusb {
+ status = "okay";
+ renesas,enable-gpio = <&gpio5 18 GPIO_ACTIVE_HIGH>;
+};
As I said before, this is not enough. We need pinctrl-related props. Same
is true for other boards.
Thank you very much for the point again.
Finally I understood what you said before.
I will start studying the pinctrl world.
Looks like it will be quicker if I post v3 of your patches.
Unfortunately, there'll be pinctrl-related error messages in the log if
the internal PCI and HS-USB drivers are enabled together but everything should
still work.
Best regards,
Yoshihiro Shimoda
WBR, Sergei
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