On Tuesday 21 October 2014 02:37 PM, Sebastian Hesselbarth wrote: > Currently, Berlin SATA PHY driver assumes PHY_BASE address being > constant. While this PHY_BASE is correct for BG2Q, older BG2 PHY_BASE > is different. Prepare the driver for BG2 support by moving the phy_base > into private driver data. > > Acked-by: Antoine Ténart <[email protected]> > Signed-off-by: Sebastian Hesselbarth <[email protected]> > --- > Cc: Kishon Vijay Abraham I <[email protected]> > Cc: "Antoine Ténart" <[email protected]> > Cc: [email protected] > Cc: [email protected] > Cc: [email protected] > --- > drivers/phy/phy-berlin-sata.c | 42 ++++++++++++++++++++++++++++-------------- > 1 file changed, 28 insertions(+), 14 deletions(-) > > diff --git a/drivers/phy/phy-berlin-sata.c b/drivers/phy/phy-berlin-sata.c > index 69ced52d72aa..9682b0f66177 100644 > --- a/drivers/phy/phy-berlin-sata.c > +++ b/drivers/phy/phy-berlin-sata.c > @@ -30,7 +30,7 @@ > #define MBUS_WRITE_REQUEST_SIZE_128 (BIT(2) << 16) > #define MBUS_READ_REQUEST_SIZE_128 (BIT(2) << 19) > > -#define PHY_BASE 0x200 > +#define BG2Q_PHY_BASE 0x200 > > /* register 0x01 */ > #define REF_FREF_SEL_25 BIT(0) > @@ -61,15 +61,16 @@ struct phy_berlin_priv { > struct clk *clk; > struct phy_berlin_desc **phys; > unsigned nphys; > + u32 phy_base; > }; > > -static inline void phy_berlin_sata_reg_setbits(void __iomem *ctrl_reg, u32 > reg, > - u32 mask, u32 val) > +static inline void phy_berlin_sata_reg_setbits(void __iomem *ctrl_reg, > + u32 phy_base, u32 reg, u32 mask, u32 val) > { > u32 regval; > > /* select register */ > - writel(PHY_BASE + reg, ctrl_reg + PORT_VSR_ADDR); > + writel(phy_base + reg, ctrl_reg + PORT_VSR_ADDR); > > /* set bits */ > regval = readl(ctrl_reg + PORT_VSR_DATA); > @@ -103,17 +104,20 @@ static int phy_berlin_sata_power_on(struct phy *phy) > writel(regval, priv->base + HOST_VSA_DATA); > > /* set PHY mode and ref freq to 25 MHz */ > - phy_berlin_sata_reg_setbits(ctrl_reg, 0x1, 0xff, > - REF_FREF_SEL_25 | PHY_MODE_SATA); > + phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01, > + 0x00ff, REF_FREF_SEL_25 | PHY_MODE_SATA); > > /* set PHY up to 6 Gbps */ > - phy_berlin_sata_reg_setbits(ctrl_reg, 0x25, 0xc00, PHY_GEN_MAX_6_0); > + phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25, > + 0x0c00, PHY_GEN_MAX_6_0); > > /* set 40 bits width */ > - phy_berlin_sata_reg_setbits(ctrl_reg, 0x23, 0xc00, DATA_BIT_WIDTH_40); > + phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x23, > + 0x0c00, DATA_BIT_WIDTH_40); > > /* use max pll rate */ > - phy_berlin_sata_reg_setbits(ctrl_reg, 0x2, 0x0, USE_MAX_PLL_RATE); > + phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x02, > + 0x0000, USE_MAX_PLL_RATE); > > /* set Gen3 controller speed */ > regval = readl(ctrl_reg + PORT_SCR_CTL); > @@ -182,9 +186,22 @@ static u32 phy_berlin_power_down_bits[] = { > POWER_DOWN_PHY1, > }; > > +static u32 bg2q_sata_phy_base = BG2Q_PHY_BASE; > + > +static const struct of_device_id phy_berlin_sata_of_match[] = { > + { > + .compatible = "marvell,berlin2q-sata-phy", > + .data = &bg2q_sata_phy_base,
Can't the base directly come from dt? Thanks Kishon -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
