On Thursday, December 18, 2014 7:16 AM, Arnd Bergmann wrote: > On Wednesday 17 December 2014 11:34:45 Gabriel FERNANDEZ wrote: > > ST sti SoCs PCIe IPs are built around DesignWare IP Core. > > But in these SoCs PCIe IP doesn't support IO.
Hi Gabriel, I cannot understand how ST sti SoCs PCIe IP does not support I/O. As far as I know, it cannot be selected by the 'parameter'. Then, H/W engineers dropped out the I/O control logic? > > > > To support this, add setup_bus() to pcie_host_ops. > > > > Signed-off-by: Fabrice Gasnier <[email protected]> > > Signed-off-by: Gabriel Fernandez <[email protected]> > > The dw-pcie driver should be able to tell whether the device has > an I/O space or not, and do the right thing based on that. Don't > add an implementation specific callback for that. I agree with Arnd's opinion. In addition, I have one more question. Then, if a device that requires I/O region is connected to PCIe slot of ST sti SoCs PCIe, what will happen? It just prints error messages? Best regards, Jingoo Han > > Arnd -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
