Describe the L1 cache in the CPU node: - L1 instruction cache: 32 KiB (8 KiB x 4 ways), - L1 data cache: 32 KiB (8 KiB x 4 ways).
Add a link to the L2 cache. Signed-off-by: Geert Uytterhoeven <[email protected]> --- v2: - New. --- arch/arm/boot/dts/r8a7740.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index c84a99931e30304c..81c26cf63ba0e78d 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -26,6 +26,15 @@ reg = <0x0>; clock-frequency = <800000000>; power-domains = <&pd_a3sm>; + i-cache-size = <0x8000>; + i-cache-sets = <256>; + i-cache-block-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <256>; + d-cache-block-size = <32>; + d-cache-line-size = <32>; + next-level-cache = <&L2>; }; }; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
