On Tue, Feb 24, 2015 at 1:56 AM, Michal Simek <[email protected]> wrote:
> Initial version of device tree for Xilinx ZynqMP SoC.
>
> Signed-off-by: Michal Simek <[email protected]>
> Acked-by: Sören Brinkmann <[email protected]>
> ---
[...]
> + gic: interrupt-controller@f9010000 {
> + compatible = "arm,cortex-a15-gic",
> "arm,cortex-a9-gic";
gic-400, right?
> + #interrupt-cells = <3>;
> + reg = <0x0 0xf9010000 0x10000>,
> + <0x0 0xf9020000 0x20000>,
> + <0x0 0xf9040000 0x20000>,
> + <0x0 0xf9060000 0x20000>;
These addresses are wrong if you are doing address swizzling to do 64K
offsets. We don't really have an answer yet as to what is the right
way. See the XGene GIC discussion[1].
Rob
[1] https://www.mail-archive.com/[email protected]/msg62547.html
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