Hi Richard,
On 25/02/15 17:01, Richard Cochran wrote:
On Wed, Feb 25, 2015 at 04:19:45PM +0100, Richard Cochran wrote:
Let me suggest another approach that stays in line with the existing
frame work. Based on the device's limitations and your own example,
it seems clear that the intended use case is synchronization for AVB
applications using gPTP.
Also, forgot to say, expose your clock as a PTP Hardware Clock (PHC).
Regarding this last point, the actual counter that generates the
timestamps is not part of the sniffer H/W module. Timestamps are
provided to the sniffer externally in H/W by a different module.
Apart of that there is not eg. a sniffer register to read the current
counter value. I wonder if it should be the driver for the module where
the counter belongs (called Event Timer in the Pistachio Soc) that
should register the PHC.
I need some more time to study your other suggestions regarding the PHY
timestamping framework.
Thanks,
Richard
Regards,
Stathis
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