On Tue, 2015-03-10 at 17:22 -0500, Thor Thayer wrote:
> > However, I'm now considering what if we just replace
> > dw_{write/read}w() by l-variants without any additional DT property
> > and accessor functions?
> > Would it work for both your cases (old chip, new chip)?
> > On my side I may test this on Intel MID.
> >
>
> Yes, this would be the simplest solution. The l-variant certainly works
> on our legacy SoCs. I'll be curious to hear your testing results.
Whenever you send a new version of patch.
> The data sheet mentions that registers are addressed at 32-bit
> boundaries to remain consistent with the AHB bus (Section 6.1 of
> dw_apb_ssi_db.pdf). Additionally unused bits are reserved for writes
> and 0 for reads so this seems like a good solution.
>
> My concern is the presence of legacy devices that I have no way of
> testing. Is a Request For Test in the body of the patch sufficient?
Better to write this wider in cover letter or (in case of one patch) in
additional description usually located after '---' line.
Since I fixed couple of bugs in core I'm not sure we have a lot of
users. Nevertheless, can you check who was recent and / or active
contributor to spi-dw-mmio.c and put him / her to Cc list.
--
Andy Shevchenko <[email protected]>
Intel Finland Oy
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