This adds support for the Imagination Technologies hash accelerator which
provides hardware acceleration for SHA1 SHA244 SHA256 and MD5 hashes.
Tested on silicon, using testmgr.
Changes from V3:
* Standardised the cra_priorities to 300, sufficient to be chosen
ahead of software / assembly implementations.
* Addressed Andrew Bresticker's review comments, except for two items
that I will leave for when I have some more bandwidth if possible as
I don't think they are required:
->Runtime PM
->Threaded IRQ handler instead of a tasklet
Changes from V2:
* This hardware does not support importing a partial hash state,
so the init, update, final and finup have been reworked to use
a fallback driver; only digest remains as hardware accelerated.
* Simplified the driver as a result of the above rework
Changes from V1:
* Addressed review comments from Andrew Bresticker and
Vladimir Zapolskiy
* rebased to current linux-next
James Hartley (2):
This adds support for the Imagination Technologies hash accelerator
which provides hardware acceleration for SHA1 SHA224 SHA256 and
MD5 hashes.
This adds the binding documentation for the Imagination Technologies
hash accelerator that provides hardware acceleration for
SHA1/SHA224/SHA256/MD5 hashes. This hardware will be present
in the upcoming pistachio SoC.
.../devicetree/bindings/crypto/img-hash.txt | 27 +
drivers/crypto/Kconfig | 14 +
drivers/crypto/Makefile | 1 +
drivers/crypto/img-hash.c | 1026 ++++++++++++++++++++
4 files changed, 1068 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/img-hash.txt
create mode 100644 drivers/crypto/img-hash.c
--
1.7.9.5
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