On Monday 16 March 2015 13:00:51 Kumar Gala wrote:
> On Mar 16, 2015, at 9:20 AM, Gabriel FERNANDEZ <[email protected]>
> wrote:
>
> > ST sti SoCs PCIe IPs are built around DesignWare IP Core.
> > But in these SoCs PCIe IP doesn't support IO.
> >
> > This patch adds the possibility to disable it through
> > a DT property, by creating an empty IO window and by
> > removing PCI_COMMAND_IO from the setup register.
> >
> > Signed-off-by: Fabrice Gasnier <[email protected]>
> > Signed-off-by: Gabriel Fernandez <[email protected]>
> > ---
> > .../devicetree/bindings/pci/designware-pcie.txt | 2 ++
> > drivers/pci/host/pcie-designware.c | 24
> > ++++++++++++++++++++--
> > drivers/pci/host/pcie-designware.h | 1 +
> > 3 files changed, 25 insertions(+), 2 deletions(-)
>
> Why not just update the code such that if the ranges doesn’t have an IO
> space rather than introducing a new DT property?
I suspect we can simplify this now by changing over the designware PCI
code from pci_common_init_dev to calling pci_scan_root_bus() in the
same way that pci-versatile.c does. This would also clean up some
other areas of the driver and let you do proper error handling
in the probe.
Arnd
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