On Tue 01 Sep 01:18 PDT 2015, Stanimir Varbanov wrote:
> On 08/27/2015 08:37 PM, Bjorn Andersson wrote:
> > This documents a device tree binding for exposing the Qualcomm Shared
> > Memory State Machine as a set of gpio- and interrupt-controllers.
> >
> > Signed-off-by: Bjorn Andersson <[email protected]>
> > ---
> > .../devicetree/bindings/gpio/qcom,smsm.txt | 114
> > +++++++++++++++++++++
>
> <snip>
>
> > += EXAMPLE
> > +The following example shows the SMEM setup for controlling properties of
> > the
> > +wireless processor, defined from the 8974 apps processor's point-of-view.
> > It
> > +encompasses one outbound entry and the outgoing interrupt for the wireless
> > +processor.
> > +
> > +smsm {
> > + compatible = "qcom,smsm";
> > +
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + qcom,ipc-3 = <&apcs 8 19>;
>
> Can we use something more descriptive here, for example
>
> qcom,ipc-rpm = <&apcs 8 19>;
Not really, because in the view of smsm we don't now which host the rpm
would represent. But most likely 3 would mean WCNSS, per the enum in
caf.
>
> and replace these magic numbers with defines?
>
I don't know what those defines would be named, what you have here is
bit 19 in the 8th byte - straight from the register documentation.
> > +
> > + apps_smsm: apps@0 {
> > + reg = <0>;
> > +
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + };
> > +
> > + wcnss_smsm: wcnss@7 {
> > + reg = <7>;
> > + interrupts = <0 144 1>;
> > +
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + };
> > +};
Regards,
Bjorn
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